公开(公告)号：US12266589B2

公开(公告)日：2025-04-01

申请号：US18635894

申请日：2024-04-15

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US12087731B2

公开(公告)日：2024-09-10

申请号：US18127539

申请日：2023-03-28

Applicant: Intel Corporation

Inventor： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Ram S. Viswanath ,  Nicholas Neal ,  Mitul Modi

IPC: H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.

公开(公告)号：US11854935B2

公开(公告)日：2023-12-26

申请号：US16794789

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L25/065 ,  H01L23/367

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US11804418B2

公开(公告)日：2023-10-31

申请号：US16246311

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Je-Young Chang ,  Jae Kim ,  Ravindranath Mahajan

IPC: H05K7/20 ,  H01L23/433 ,  F28F3/12 ,  F28F9/00 ,  H01L23/367 ,  H01L23/473 ,  F28F9/02 ,  F28D21/00

CPC classification number: H01L23/4336 ,  F28F3/12 ,  F28F9/001 ,  F28F9/0202 ,  H01L23/367 ,  H01L23/4735 ,  H05K7/20254 ,  F28D2021/0029 ,  F28F2260/02

Abstract: A heat exchange module, comprising an array of microchannels, where the array of microchannels extends in a first direction, and are separated from one another by a first sidewall. The array of microchannels is over a cold plate. A first array of fluid distribution channels is stacked over the array of microchannels and extend in a second direction that is substantially orthogonal to the first direction. The first array of fluid distribution channels extends from the first manifold and terminate between a first manifold and a second manifold. A second array of fluid distribution channels is stacked over the array of microchannels. The first array of fluid distribution channels and the second array of the fluid distribution channels are fluidically coupled to the microchannel array. A wall extends into the microchannel array below a second sidewall separating ones of the first array and ones of the second array of fluid distribution channels.

公开(公告)号：US11640929B2

公开(公告)日：2023-05-02

申请号：US16227201

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Nicholas Neal ,  Divya Mani ,  Nicholas Haehn

IPC: H01L23/00 ,  H01L23/473 ,  H01L23/498 ,  H01L23/467 ,  H01L21/48

Abstract: An integrated circuit assembly may be formed having a substrate core, wherein the substrate core includes at least one heat transfer fluid channel formed therein, a first build-up layer formed on a first surface of the substrate core, and a second build-up layer formed on a second surface of the substrate core, and methods of fabricating the same. In embodiments of the present description, the integrated circuit structure may include at least one integrated circuit device formed within at least one of the first build-up layer and the second build-up layer. The embodiments of the present description allow for cooling within the substrate, which may significantly reduce thermal damage to the components of the substrate and/or integrated circuit devices within the substrate.

公开(公告)号：US20210249330A1

公开(公告)日：2021-08-12

申请号：US16783804

申请日：2020-02-06

Applicant: Intel Corporation

Inventor： Nicholas S. Haehn ,  Nicholas Neal

IPC: H01L23/367 ,  H01L23/473 ,  H01L21/50

Abstract: Embodiments herein relate to systems, techniques, and/or processes directed to a composite thermal matrix structure to provide thermal conductivity within a package. The composite thermal matrix may include a first material that is substantially solid and a second material that is liquid and absorbed into the first material. A package may include the composite thermal matrix within an integrated heat sink coupled with a printed circuit board and encapsulating one or more die where the thermal matrix structure is in a state of compressive stress within the heat sink. The thermal matrix structure may expand and contract as the heat sink warps during thermal cycling to maintain constant thermal conductivity with low stress on the package.

公开(公告)号：US12057369B2

公开(公告)日：2024-08-06

申请号：US18088478

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Weston Bertrand ,  Kyle Arrington ,  Shankar Devasenathipathy ,  Aaron McCann ,  Nicholas Neal ,  Zhimin Wan

IPC: H01L23/433 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/433 ,  H01L23/3675 ,  H01L25/0657

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

公开(公告)号：US12009271B2

公开(公告)日：2024-06-11

申请号：US16511360

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Edvin Cetegen ,  Jacob Vehonsky ,  Nicholas S. Haehn ,  Thomas Heaton ,  Steve S. Cho ,  Rahul Jain ,  Tarek Ibrahim ,  Antariksh Rao Pratap Singh ,  Nicholas Neal ,  Sergio Chan Arguedas ,  Vipul Mehta

IPC: H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/18161

Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.

公开(公告)号：US11942393B2

公开(公告)日：2024-03-26

申请号：US16781563

申请日：2020-02-04

Applicant: Intel Corporation

Inventor： Wei Li ,  Edvin Cetegen ,  Nicholas S. Haehn ,  Mitul Modi ,  Nicholas Neal

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L23/3735 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/16 ,  H01L24/81 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2224/16225 ,  H01L2224/81203

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.

公开(公告)号：US11587843B2

公开(公告)日：2023-02-21

申请号：US16219158

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Prasad Ramanathan ,  Nicholas Neal ,  Chandra Mohan Jha

IPC: H01L23/34 ,  H01L23/52 ,  H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L23/373

Abstract: Integrated circuit IC package with one or more IC dies including solder features that are thermally coupled to the IC. The thermally coupled solder features (e.g., bumps) may be electrically insulated from solder features electrically coupled to the IC, but interconnected with each other by one or more metallization layers within a plane of the IC package. An in-plane interconnected network of thermal solder features may improve lateral heat transfer, for example spreading heat from one or more hotspots on the IC die. An under-bump metallization (UBM) may interconnect two or more thermal solder features. A through-substrate via (TSV) metallization may interconnect two or more thermal solder features. A stack of IC dies may include thermal solder features interconnected by metallization within one or more planes of the stack.