公开(公告)号：US11444024B2

公开(公告)日：2022-09-13

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US09391019B2

公开(公告)日：2016-07-12

申请号：US14220814

申请日：2014-03-20

Applicant: Intel Corporation

Inventor： Mauro Kobrinsky ,  Tatyana Andryushchenko ,  Ramanan Chebiam ,  Hui Jae Yoo

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures including a selective via post disposed on a top surface of a lower level interconnect feature, and fabrication techniques to selectively form such a post. Following embodiments herein, a minimum interconnect line spacing may be maintained independent of registration error in a via opening. In embodiments, a selective via post has a bottom lateral dimension smaller than that of a via opening within which the post is disposed. Formation of a conductive via post may be preferential to a top surface of the lower interconnect feature exposed by the via opening. A subsequently deposited dielectric material backfills portions of a via opening extending beyond the interconnect feature where no conductive via post was formed. An upper level interconnect feature is landed on the selective via post to electrically interconnect with the lower level feature.

Abstract translation: 互连结构，包括设置在下层互连特征的顶表面上的选择通孔，以及选择性地形成这种柱的制造技术。 以下实施例中，可以独立于通孔开口中的配准误差来维持最小互连线间距。 在实施例中，选择性通孔支柱的底部横向尺寸小于通孔开口的底部横向尺寸，在该通孔开口内设置有支柱。 导电通孔的形成可优先于由通孔开口暴露的下互连特征的顶表面。 随后沉积的电介质材料回填了超过互连特征的通孔开口的部分，其中没有形成导电通孔。 上级互连功能着陆在选择性通孔上以与较低级别特征电互连。