公开(公告)号：US12278289B2

公开(公告)日：2025-04-15

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Tanay Gosavi ,  Ashish Verma Penumatcha ,  Shriram Shivaraman ,  Chia-Ching Lin ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US12266720B2

公开(公告)日：2025-04-01

申请号：US17129486

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Chelsey Dorow ,  Kevin O'Brien ,  Sudarat Lee ,  Kirby Maxey ,  Ashish Verma Penumatcha ,  Tanay Gosavi ,  Patrick Theofanis ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Shriram Shivaraman

IPC: H01L29/76 ,  H01L21/02 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24

Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

公开(公告)号：US11532558B2

公开(公告)日：2022-12-20

申请号：US16585666

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Mauro Kobrinsky ,  Richard Vreeland ,  Ramanan Chebiam ,  William Brezinski ,  Brennen Mueller ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/768

Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.

公开(公告)号：US20220199783A1

公开(公告)日：2022-06-23

申请号：US17133087

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Tanay Gosavi ,  Sudarat Lee ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Uygar Avci

IPC: H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/22 ,  H01L27/24

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

公开(公告)号：US20210351105A1

公开(公告)日：2021-11-11

申请号：US17303270

申请日：2021-05-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish AGRAWAL ,  Urusa ALAAN ,  Christopher JEZEWSKI ,  Mauro KOBRINSKY ,  Kevin LIN ,  Abhishek Anil SHARMA

IPC: H01L23/40 ,  H01L21/70 ,  H01L21/822 ,  H01L27/12 ,  H01L23/532

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US11164809B2

公开(公告)日：2021-11-02

申请号：US16221815

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L27/12 ,  H01L23/40 ,  H01L21/70 ,  H01L21/822 ,  H01L23/532

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US12266712B2

公开(公告)日：2025-04-01

申请号：US17133087

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Tanay Gosavi ,  Sudarat Lee ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Uygar Avci

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H10B61/00 ,  H10B63/00 ,  H10N50/85 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

公开(公告)号：US12165917B2

公开(公告)日：2024-12-10

申请号：US17087521

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Christopher Jezewski

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Integrated circuit interconnect structures including an interconnect metallization feature with a barrier material comprising a metal and a chalcogen. Introduction of the chalcogen may improve diffusion barrier properties at a given barrier material layer thickness with increasing the barrier layer thickness. A barrier material, such as TaN, may be deposited at minimal thickness, and doped with a chalcogen before or after one or more fill materials are deposited over the barrier material. During thermal processing mobile chalcogen impurities may collect within regions within the barrier material to high enough concentrations for at least a portion of the barrier material to be converted into a metal chalcogenide layer. The metal chalcogenide layer may have greater crystallinity than a remainder of the barrier layer.

公开(公告)号：US12125895B2

公开(公告)日：2024-10-22

申请号：US16915600

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Kevin O'Brien ,  Carl Naylor ,  Uygar Avci ,  Sudarat Lee ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Tanay Gosavi ,  Shriram Shivaraman ,  Kirby Maxey

IPC: H01L29/66 ,  B82Y10/00 ,  B82Y25/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B63/00 ,  H10N70/20

CPC classification number: H01L29/66439 ,  H01L21/02568 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/78696 ,  H10B63/30 ,  H10B63/34 ,  H10N70/253

Abstract: A transistor includes a channel including a first layer including a first monocrystalline transition metal dichalcogenide (TMD) material, where the first layer is stoichiometric and includes a first transition metal. The channel further includes a second layer above the first layer, the second layer including a second monocrystalline TMD material, where the second monocrystalline TMD material includes a second transition metal and oxygen, and where the second layer is sub-stoichiometric. The transistor further includes a gate electrode above a first portion of the channel layer, a gate dielectric layer between the channel layer and the gate electrode, a source contact on a second portion of the channel layer and a drain contact on a third portion of the channel layer, where the gate electrode is between drain contact and the source contact.

公开(公告)号：US11482622B2

公开(公告)日：2022-10-25

申请号：US16214706

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Kevin Lin ,  Abhishek Sharma ,  Carl Naylor ,  Urusa Alaan ,  Christopher Jezewski ,  Ashish Agrawal

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/24 ,  H01L29/417

Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.