公开(公告)号：US20230315501A1

公开(公告)日：2023-10-05

申请号：US17711770

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Rangeen Basu Roy Chowdhury ,  Matthew C. Merten ,  Jason M. Agron ,  Tyler N. Sondag ,  Gregory A. Woods

IPC: G06F9/455

CPC classification number: G06F9/4552 ,  G06F9/45525

Abstract: Systems, methods, and devices for original code emulation for performance monitoring is provided. A system may memory to store instructions. A processor may implement an instruction converter in hardware or software to convert the instructions to translated code. Specifically, the instruction converter receives the instructions and translates the stored instructions into the translated code that includes one or more indexed instructions. The one or more indexed instructions include a field indicating a number of branches in the stored instructions that are taken in the translated code.

公开(公告)号：US11372775B2

公开(公告)日：2022-06-28

申请号：US16777063

申请日：2020-01-30

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jason M. Agron ,  Cristiano Pereira ,  Rangeen Basu Roy Chowdhury

IPC: G06F12/10 ,  G06F12/12 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/32 ,  G06F12/0831 ,  G06F9/38 ,  G06F8/00 ,  G06F12/02

Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

公开(公告)号：US20200174944A1

公开(公告)日：2020-06-04

申请号：US16777063

申请日：2020-01-30

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jason M. Agron ,  Cristiano Pereira ,  Rangeen Basu Roy Chowdhury

IPC: G06F12/1027 ,  G06F9/38 ,  G06F12/0831 ,  G06F9/32 ,  G06F12/12 ,  G06F12/1009 ,  G06F12/02 ,  G06F8/00

Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

公开(公告)号：US20190179766A1

公开(公告)日：2019-06-13

申请号：US15839310

申请日：2017-12-12

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jason M. Agron ,  Cristiano Pereira ,  Glenn Hinton ,  Sebastian Winkel ,  Rangeen Basu Roy Chowdhury

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F9/30

Abstract: A processor comprising an instruction execution circuit to execute a translated code generated based on a received code and a translation table (TT) controller circuit coupled to a translation table comprising a plurality of address mappings, wherein the TT controller circuit is to identify a trigger event associated with a physical memory page, determine, based on an identifier of the physical memory page, an entry in a manifest table, the entry comprising an address mapping between a first memory address within an address range comprising the physical memory page and a second memory address, and store the address mapping to the translation table.