公开(公告)号：US10437590B2

公开(公告)日：2019-10-08

申请号：US15719290

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Sofia Pediaditaki ,  Ethan Schuchman ,  Rangeen Basu Roy Chowdhury ,  Manjunath Shevgoor

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/0846 ,  G06F12/128 ,  G06F9/52 ,  G06F12/0811

Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.

公开(公告)号：US11048318B2

公开(公告)日：2021-06-29

申请号：US16370572

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Julien Sebot ,  Rangeen Basu Roy Chowdhury ,  Rustam Miftakhutdinov ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Eric Donkoh

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/324 ,  G06N20/00 ,  G06F9/50 ,  G06N5/04 ,  G06F1/3228

Abstract: A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.

公开(公告)号：US20190188154A1

公开(公告)日：2019-06-20

申请号：US15843165

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Rangeen Basu Roy Chowdhury ,  Hussein Elnawawy ,  Amro Awad

IPC: G06F12/126 ,  G06F12/1027 ,  G06F12/1018 ,  G06F9/30 ,  G06F9/50 ,  G06F9/455

CPC classification number: G06F12/126 ,  G06F9/3004 ,  G06F9/5016 ,  G06F12/1018 ,  G06F12/1027 ,  G06F2009/45583 ,  G06F2212/684

Abstract: A processor includes a first translation lookaside buffer (TLB), a second TLB, and a TLB control mechanism. The TLB control mechanism is to store a TLB-miss count (TMC) for a page. The TMC indicates a number of TLB misses of the first TLB for the page. The TLB control mechanism is further to determine that the TMC is greater than a threshold count and store a translation of the page in the second TLB responsive to a determination that the TMC is greater than the threshold count.

公开(公告)号：US20220413870A1

公开(公告)日：2022-12-29

申请号：US17304775

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Vineeth Thamarassery Mekkat ,  Sebastian Christoph Albert Winkel ,  Rangeen Basu Roy Chowdhury

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/30

Abstract: An apparatus comprises decoder circuitry to decode an instruction that includes an opcode to indicate a protected load operation, a source field for source memory address information, and a destination field to identify a destination register. The apparatus also comprises memory to store an allocate load-protect (LP) data structure with an entry for the identified destination register. The entry comprises an IP field and a status field. The apparatus also comprises load elision circuitry to (a) use the allocate LP data structure to determine whether the identified destination register has active status for the IP; (b) in response to determining that the identified destination register has active status for the IP, cause the instruction to be elided; and (c) in response to determining that the identified destination register does not have active status for the IP, cause the instruction to be executed. Other embodiments are described and claimed.

公开(公告)号：US20190163642A1

公开(公告)日：2019-05-30

申请号：US15823387

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jason M. Agron ,  Cristiano Pereira ,  Rangeen Basu Roy Chowdhury

IPC: G06F12/1027 ,  G06F12/1009 ,  G06F12/12 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0831

Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

公开(公告)号：US20190095203A1

公开(公告)日：2019-03-28

申请号：US15719290

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Sofia Pediaditaki ,  Ethan Schuchman ,  Rangeen Basu Roy Chowdhury ,  Manjunath Shevgoor

IPC: G06F9/30 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/0811 ,  G06F9/52

CPC classification number: G06F9/3004 ,  G06F9/30036 ,  G06F9/524 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0848 ,  G06F12/0875 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/282 ,  G06F2212/283 ,  G06F2212/6042 ,  G06F2212/621

Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.

公开(公告)号：US12169718B2

公开(公告)日：2024-12-17

申请号：US17304775

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Vineeth Thamarassery Mekkat ,  Sebastian Christoph Albert Winkel ,  Rangeen Basu Roy Chowdhury

IPC: G06F9/38 ,  G06F8/41 ,  G06F9/30 ,  G06F9/50

Abstract: An apparatus comprises decoder circuitry to decode an instruction that includes an opcode to indicate a protected load operation, a source field for source memory address information, and a destination field to identify a destination register. The apparatus also comprises memory to store an allocate load-protect (LP) data structure with an entry for the identified destination register. The entry comprises an IP field and a status field. The apparatus also comprises load elision circuitry to (a) use the allocate LP data structure to determine whether the identified destination register has active status for the IP; (b) in response to determining that the identified destination register has active status for the IP, cause the instruction to be elided; and (c) in response to determining that the identified destination register does not have active status for the IP, cause the instruction to be executed. Other embodiments are described and claimed.

公开(公告)号：US20240111539A1

公开(公告)日：2024-04-04

申请号：US17957969

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jason Agron ,  Andreas Kleen ,  Rangeen Basu Roy Chowdhury

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30189

Abstract: Techniques and mechanisms for a processor to determine an operational mode based on metadata for a page table. In an embodiment, an instruction fetch unit of the processor detects a pointer to a next instruction, in a sequence of instructions, which is to be prepared for execution with a core of the processor. Based on the pointer, a page table is identified as including an entry which indicates a location of the instruction. The page table includes, or otherwise corresponds to, metadata which comprises an identifier of an operational mode of the processor. Based on the metadata, the processor is transitioned to the operational mode in preparation for an execution of the instruction. In another embodiment, the operational mode is one of multiple operational modes which each correspond to a different instruction set architecture.

公开(公告)号：US20230315473A1

公开(公告)日：2023-10-05

申请号：US17712139

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Muhammad Azeem ,  Rangeen Basu Roy Chowdhury ,  Xiang Zou ,  Malihe Ahmadi ,  Joju Joseph Zajo ,  Ariel Sabba ,  Ammon Christiansen ,  Polychronis Xekalakis ,  Eliyah Kilada

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/382 ,  G06F9/3873 ,  G06F9/30149

Abstract: Embodiments of apparatuses and methods for variable-length instruction steering to instruction decode clusters are disclosed. In an embodiment, an apparatus includes a decode cluster and chunk steering circuitry. The decode cluster includes multiple instruction decoders. The chunk steering circuitry is to break a sequence of instruction bytes into a plurality of chunks, create a slice from a one or more of the plurality of chunks based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks, wherein the slice has a variable size and includes a plurality of instructions, and steer the slice to the decode cluster.

公开(公告)号：US20200183482A1

公开(公告)日：2020-06-11

申请号：US16370572

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Julien Sebot ,  Rangeen Basu Roy Chowdhury ,  Rustam Miftakhutdinov ,  Stephen J. Tarsa ,  Gautham N. Chinya ,  Eric Donkoh

IPC: G06F1/3234 ,  G06F1/3296 ,  G06F1/324 ,  G06F1/3228 ,  G06F9/50 ,  G06N5/04 ,  G06N20/00

Abstract: A system on a chip is described that comprises a processor and a set of memory components that store instructions, which when executed by the processor cause the system on a chip to: generate, by a set of data collectors of a telemetry subsystem, a set of streams of telemetry metadata describing operation of the processor, forward one or more streams of telemetry metadata from the set of streams of telemetry metadata to a set of machine learning-driven adaptation decision models, receive, from the set of machine learning-driven adaptation decision models, a set of configuration parameters for controlling operation of the processor based on the one or more streams of telemetry metadata, and modify operation of the processor based on the set of configuration parameters.