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    HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES
    14.
    发明申请
    HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES 有权

    公开(公告)号：US20230103000A1

    公开(公告)日：2023-03-30

    申请号：US17485386

    申请日：2021-09-25

    Applicant: Intel Corporation

    Inventor： Rupin Vakharwala ,  Prashant Sethi ,  Rajesh M. Sankaran ,  Philip R. Lantz ,  David J. Harriman ,  Utkarsh Y. Kakaiya ,  Vinay Raghav ,  Ashok Raj ,  Siva Bhanu Krishna Boga

    IPC: G06F12/1027 ,  G06F12/0802 ,  G06F13/42

    Abstract: Embodiments of apparatuses, methods, and systems for hardware manage address translation services are described. In an embodiment, an apparatus includes a first interconnect, a second interconnect, address translation hardware, a device, a translation lookaside buffer. The address translation hardware is coupled to the interconnect and is to provide a translation of a first address to a second address. The device is coupled to the first interconnect and the second interconnect and is to provide the first address to the address translation hardware through the first interconnect. The translation lookaside buffer includes an entry to store the translation, which is to be provided to the translation lookaside buffer through the first interconnect by the address translation hardware. The device is to access a system memory through the second interconnect using the second address from the entry in the translation lookaside buffer. The second interconnect is in the only path between the device and the system memory.

    Apparatus and method to identify the source of an interrupt
    17.
    发明授权
    Apparatus and method to identify the source of an interrupt 有权

    公开(公告)号：US11048512B1

    公开(公告)日：2021-06-29

    申请号：US16833598

    申请日：2020-03-28

    Applicant: Intel Corporation

    Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

    IPC: G06F9/50 ,  G06F9/30 ,  G06F15/80 ,  G06F9/48

    Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

    SECURE ADDRESS TRANSLATION SERVICES USING MESSAGE AUTHENTICATION CODES AND INVALIDATION TRACKING
    18.
    发明申请
    SECURE ADDRESS TRANSLATION SERVICES USING MESSAGE AUTHENTICATION CODES AND INVALIDATION TRACKING 审中-公开

    公开(公告)号：US20200026661A1

    公开(公告)日：2020-01-23

    申请号：US16582919

    申请日：2019-09-25

    Applicant: Intel Corporation

    Inventor： Michael Kounavis ,  David Koufaty ,  Anna Trikalinou ,  Rupin Vakharwala

    IPC: G06F12/1027 ,  G06F12/0831 ,  G06F12/0868 ,  G06F12/14 ,  G11C15/04

    Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes a memory for storage of data, an Input/Output Memory Management Unit (IOMMU) coupled to the memory via a host-to-device link the IOMMU to perform operations, comprising receiving a memory access request from a remote device via a host-to-device link, wherein the memory access request comprises a host physical address (HPA) that identifies a physical address within the memory pertaining to the memory access request and a first message authentication code (MAC), generating a second message authentication code (MAC) using the host physical address received with the memory access request and a private key associated with the remote device, and performing at least one of allowing the memory access to proceed when the first MAC and the second MAC match and the HPA is not in an invalidation tracking table (ITT) maintained by the IOMMU; or blocking the memory operation when the first MAC and the second MAC do not match.

    SECURE ADDRESS TRANSLATION SERVICES USING A PERMISSION TABLE
    19.
    发明申请
    SECURE ADDRESS TRANSLATION SERVICES USING A PERMISSION TABLE 审中-公开

    公开(公告)号：US20200019515A1

    公开(公告)日：2020-01-16

    申请号：US16582956

    申请日：2019-09-25

    Applicant: Intel Corporation

    Inventor： David Koufaty ,  Rajesh Sankaran ,  Anna Trikalinou ,  Rupin Vakharwala

    IPC: G06F12/14 ,  G06F12/0862 ,  G06F12/1009 ,  G06F13/16 ,  G06F13/42

    Abstract: Embodiments are directed to providing a secure address translation service. An embodiment of a system includes DRAM for storage of data, an IOMMU coupled to the DRAM, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the DRAM, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the DRAM pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the DRAM within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.

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