公开(公告)号：US11169929B2

公开(公告)日：2021-11-09

申请号：US15958591

申请日：2018-04-20

Applicant: Intel Corporation

Inventor： Rupin Vakharwala ,  Amin Firoozshahian ,  Stephen Van Doren ,  Rajesh Sankaran ,  Mahesh Madhav ,  Omid Azizi ,  Andreas Kleen ,  Mahesh Maddury ,  Ashok Raj

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/1081 ,  G06F12/1045 ,  G06F12/1027

Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

公开(公告)号：US20200311181A1

公开(公告)日：2020-10-01

申请号：US16370094

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Omid Azizi

IPC: G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06N20/00

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

公开(公告)号：US20240330402A1

公开(公告)日：2024-10-03

申请号：US18626599

申请日：2024-04-04

Applicant: Intel Corporation

Inventor： Omid Azizi

IPC: G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06N20/00

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3016 ,  G06F9/3802 ,  G06N20/00

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

公开(公告)号：US11681611B2

公开(公告)日：2023-06-20

申请号：US17119679

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Omid Azizi ,  Amin Firoozshahian ,  Andreas Kleen ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert ,  Eric Gouldey

IPC: G06F12/02 ,  G06F9/50 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0604 ,  G06F3/065 ,  G06F3/0608 ,  G06F3/0641 ,  G06F9/5016 ,  G06F12/0292

Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.

公开(公告)号：US10579551B2

公开(公告)日：2020-03-03

申请号：US15855798

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Omid Azizi ,  Chandan Egbert ,  Amin Firoozshahian ,  David Christopher Hansen ,  Andreas Kleen ,  Mahesh Maddury ,  Mahesh Madhav ,  Ashok Raj ,  Alexandre Solomatnikov ,  Stephen Van Doren

IPC: G06F13/24 ,  G06F13/16 ,  G06F3/06

Abstract: Various systems and methods for computer memory management are described herein. A system includes a memory controller to: monitor utilization of a memory device, the memory device used with a memory compression technique; determine that the utilization of the memory device violates a threshold; and initiate a system interrupt to provoke a response, responsive to the utilization of the memory device violating the threshold.

公开(公告)号：US10929503B2

公开(公告)日：2021-02-23

申请号：US16230814

申请日：2018-12-21

Applicant: Intel Corporation

Inventor： Omid Azizi ,  Chen Koren ,  Nitin Garegrat

IPC: G06F17/16 ,  G06N3/02 ,  G06F9/30

Abstract: An apparatus and method for a masked multiply instruction to support neural network pruning operations. For example, one embodiment of a processor comprises: a decoder to decode a matrix multiplication with masking (GEMM) instruction identifying a destination matrix register to store a result, and source registers storing an A-matrix, a B-matrix, and a matrix mask; execution circuitry to execute the GEMM instruction, the execution circuitry to multiply a plurality of B-matrix elements with a plurality of A-matrix elements, each of the B-matrix elements associated with a mask value in the matrix mask, wherein if the mask value is set to a first value, then the execution circuitry is to multiply the B-matrix element with one or more of the A-matrix elements to generate a first partial result, and if the mask value is set to a second value, then the execution circuitry is to multiply an alternate B-matrix element with a one or more of the A-matrix elements to generate a second partial result.

公开(公告)号：US10732880B2

公开(公告)日：2020-08-04

申请号：US15868787

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Omid Azizi ,  Amin Firoozshahian ,  John Stevenson ,  Mahesh Maddury ,  Chandan Egbert ,  Henk Neefs

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868

Abstract: Various systems and methods for computer memory management are described herein. A system for computer memory management includes a first memory device including a mapping table; a second memory device including a staging area; a third memory device including a dedup data region; and a controller operable to: receive a memory access request, the memory access request including an address and data; write the data to the staging area; and update the mapping table with the address.

公开(公告)号：US20200004677A1

公开(公告)日：2020-01-02

申请号：US16020444

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Amin Firoozshahian ,  Omid Azizi ,  Chandan Egbert ,  David Hansen ,  Andreas Kleen ,  Mahesh Maddury ,  Mahesh Madhav ,  Alexandre Solomatnikov ,  John Peter Stevenson

IPC: G06F12/02 ,  G06F12/1009 ,  G06F3/06

Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

公开(公告)号：US11977600B2

公开(公告)日：2024-05-07

申请号：US17481064

申请日：2021-09-21

Applicant: Intel Corporation

Inventor： Omid Azizi

IPC: G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06N20/00

CPC classification number: G06F17/16 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3016 ,  G06F9/3802 ,  G06N20/00

Abstract: This disclosure relates matrix operation acceleration for different matrix sparsity patterns. A matrix operation accelerator may be designed to perform matrix operations more efficiently for a first matrix sparsity pattern rather than for a second matrix sparsity pattern. A matrix with the second sparsity pattern may be converted to a matrix with the first sparsity pattern and provided to the matrix operation accelerator. By rearranging the rows and/or columns of the matrix, the sparsity pattern of the matrix may be converted to a sparsity pattern that is suitable for computation with the matrix operation accelerator.

公开(公告)号：US20210240609A1

公开(公告)日：2021-08-05

申请号：US17119679

申请日：2020-12-11

Applicant: Intel Corporation

Inventor： Omid Azizi ,  Amin Firoozshahian ,  Andreas Kleen ,  Mahesh Madhav ,  Mahesh Maddury ,  Chandan Egbert ,  Eric Gouldey

IPC: G06F12/02 ,  G06F9/50 ,  G06F3/06

Abstract: Various systems and methods for computer memory overcommitment management are described herein. A system for computer memory management includes a memory device to store data and a mapping table; and a memory overcommitment circuitry to: receive a signal to move data in a first block from a memory reduction area in the memory device to a non-memory reduction area in the memory device, the memory reduction area to store data using a memory reduction technique, and the non-memory reduction area to store data without any memory reduction techniques; allocate a second block in the non-memory reduction area; copy the data in the first block to the second block; and update the mapping table to revise a pointer to point to the second block, the mapping table used to store pointers to memory device in the memory reduction area and the non-memory reduction area.