公开(公告)号：US20170176534A1

公开(公告)日：2017-06-22

申请号：US14975691

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Sridharan Ranganathan

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31724 ,  G01R31/31716 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/3187

Abstract: Logic controlling a local link interface enables in-band self-testing of the local link interface, the connected link interface of a remote device, and the link connecting the two. Logic configures a loopback in the remote device using an in-band protocol such as MIPI. The loopback may include all the link lanes or only a selected subset. The logic then isolates the local physical layer from upstream components and causes one or more test patterns to be sent through the local link interface and through the link to the loopback. The signals returning to the local link interface from the loopback are collected and compared with the original test patterns by an on-board checker in the link interface. The results, or a metric such as BER derived from the results, can then be accessed without requiring a custom dedicated test port.

公开(公告)号：US20220317855A1

公开(公告)日：2022-10-06

申请号：US17849282

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Satheesh Chellappan ,  Antonio Cheng ,  Kar Leong Wong

IPC: G06F3/041 ,  G06N3/02

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to process touch data. An example apparatus includes machine learning accelerator circuitry to execute a machine learning algorithm on touch data from touch sensor circuitry; and determine, based on an output of the machine learning algorithm, whether a touch input corresponding to the touch data was intentional; transceiver circuitry to, after a determination that the touch input was intentional, provide touch coordinates to memory; and processor circuitry to, after the determination that the touch input was intentional: access the touch coordinates in the memory; and perform an action based on the touch coordinates.

公开(公告)号：US20190139399A1

公开(公告)日：2019-05-09

申请号：US16235807

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Srikanth Potluri

IPC: G08B29/18 ,  H04R29/00 ,  G08B3/10

Abstract: The disclosure generally provides methods, systems and apparatus for functional safety systems. Specifically, the disclosure relates to validating functional safety warnings that may be communicated to an operator. Such warnings may include safety warning chimes. An exemplary embodiment relates to an apparatus to validate operation of a Functional Safety (FuSa) platform through delivery of a safety warning signal, the apparatus comprising: a Safety Application to issue a safety warning signal, the safety warning signal configured for audio delivery to an audience; a transmit path in communication with the Safety Application to transmit the safety warning signal; and a digital signal processing (DSP) circuitry to communicate with the transmit path, the DSP circuitry configured to detect the safety warning signal at the transmit path, the DSP circuitry further configured to communicate the detected safety warning signal back to the Safety Application; wherein the transmit path, the Safety Application and the DSP circuitry are integrated on a System-on-Chip (SoC).

公开(公告)号：US20190042483A1

公开(公告)日：2019-02-07

申请号：US15941273

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Darren Abramson ,  David Hines ,  Alberto Martinez ,  Adeel Aslam ,  John Howard ,  Shanthanand R. Kutuva ,  Karthi R. Vadivelu ,  Kar Leong Wong ,  Satheesh Chellappan

IPC: G06F13/10 ,  G06F13/38

CPC classification number: G06F13/102 ,  G06F13/385 ,  G06F2209/509 ,  G06F2213/0042

Abstract: An example apparatus includes: a host controller offload capability detector to determine that a media stream offload capability is available in the peripheral interface host controller; a media stream offload arbiter to send a media stream offload request to a media processor manager based on the media stream offload capability and based on a peripheral device being connected to the peripheral interface host controller; and an endpoint mapper to generate an endpoint table entry corresponding to the peripheral device, the endpoint table entry to assign a first communication interface of the peripheral interface host controller to transfer a media stream corresponding to the peripheral device between the media processor and the peripheral interface host controller without the media stream being routed to an application processor that is in circuit with the peripheral interface host controller and in circuit with the media processor.

公开(公告)号：US10176132B2

公开(公告)日：2019-01-08

申请号：US14757830

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Chunyu Zhang

IPC: G06F13/37 ,  G06F13/42 ,  G06F1/12 ,  G06F1/26

Abstract: In a system where multiple controllers share a link interface but are not all (1) compatible with the same configuration of the physical layer or (2) using the same clocking, a configuration arbitration subsystem intercepts, organizes, and re-clocks configuration-access requests from the various controller agents. Priorities are assigned according to stored policies. The configuration arbiter grants configuration access to the top-priority agent, synchronizing the agent's message with the arbiter's clock. Lower-priority agents' messages are stored in command queues until they ascend to top priority. Besides preventing timing conflicts and streamlining the coordination of clocks, the configuration arbiter may provide access to physical-layer registers beyond the controllers' built-in capabilities to further optimize configuration.

公开(公告)号：US10139445B2

公开(公告)日：2018-11-27

申请号：US15282030

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chin Keat Teoh ,  Satheesh Chellappan ,  Lay Cheng Ong ,  Terrence Huat Hin Tan

IPC: G01R31/28 ,  G11C29/56 ,  G06F9/4401 ,  G06F11/273

Abstract: A technical solution for improving test times and costs associated with IC production includes a central test engine (CTE) functional test block integrated onto an IC. The CTE functions as a hardware abstraction layer (HAL), and provides testing capabilities by transferring a large test data file to a device under test and performing a closed-loop monitoring of receipt of the expected test data results. The CTE also reduces the number of external interfaces and interface controllers used during testing. The reduction in external interfaces reduces the size of the IC, which enables smaller and more efficient IC manufacturing, and may be used to improve small form-factor high-volume manufacturing (HVM). This reduction in IO pins also enables significant reduction in IO resources (e.g., IO drivers) within the IC, and reduces or eliminates IO test hardware dependencies.

公开(公告)号：US11308791B2

公开(公告)日：2022-04-19

申请号：US16235807

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Srikanth Potluri

IPC: G08B29/18 ,  G08B3/10 ,  H04R29/00

Abstract: The disclosure generally provides methods, systems and apparatus for functional safety systems. Specifically, the disclosure relates to validating functional safety warnings that may be communicated to an operator. Such warnings may include safety warning chimes. An exemplary embodiment relates to an apparatus to validate operation of a Functional Safety (FuSa) platform through delivery of a safety warning signal, the apparatus comprising: a Safety Application to issue a safety warning signal, the safety warning signal configured for audio delivery to an audience; a transmit path in communication with the Safety Application to transmit the safety warning signal; and a digital signal processing (DSP) circuitry to communicate with the transmit path, the DSP circuitry configured to detect the safety warning signal at the transmit path, the DSP circuitry further configured to communicate the detected safety warning signal back to the Safety Application; wherein the transmit path, the Safety Application and the DSP circuitry are integrated on a System-on-Chip (SoC).

公开(公告)号：US10606772B2

公开(公告)日：2020-03-31

申请号：US15954838

申请日：2018-04-17

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Kishore Kasichainula ,  Lay Cheng Ong ,  Chee Lim Poon ,  Harish G. Kamat

IPC: G06F9/4401 ,  G06F13/10 ,  G06F13/42

Abstract: In one example a Universal Serial Bus (USB) controller comprises at least one memory register to store one or more enumeration parameters for a USB connection with the USB controller and logic, at least partially including hardware logic, to detect a USB connection with a remote device via the USB connection, retrieve one or more connection enumeration parameters for the USB connection from the at least one memory register on the USB host controller, and implement a connection enumeration process using the one or more connection enumeration parameters retrieved from the memory register on the USB controller. Other examples may be described.

公开(公告)号：US10417170B2

公开(公告)日：2019-09-17

申请号：US15476506

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Suketu Bhatt ,  Satheesh Chellappan

IPC: G06F13/42 ,  G06F11/22 ,  G06F3/06 ,  G06F13/28

Abstract: Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.

公开(公告)号：US20170286357A1

公开(公告)日：2017-10-05

申请号：US15084555

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Anoop Mukker ,  Bharat Daga ,  David W. Vogel

IPC: G06F13/42 ,  H04L29/06

CPC classification number: G06F13/4291 ,  G06F13/4286 ,  H04L69/08

Abstract: In one embodiment, an apparatus comprises: a controller to communicate data having a format according to a first communication protocol, the controller comprising a Mobile Industry Processor Interface (MIPI)-compatible controller; an interface circuit coupled to the controller to receive the data, convert the data and communicate the converted data to a physical unit of a second communication protocol, the converted data having a format according to the second communication protocol; and the physical unit coupled to the interface circuit to receive and serialize the converted data and output the serialized converted data to a destination. Other embodiments are described and claimed.