公开(公告)号：US20230161723A1

公开(公告)日：2023-05-25

申请号：US17531522

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Satheesh Chellappan ,  Zhenyu Zhu

IPC: G06F13/38 ,  G06F13/42 ,  H02J7/00

CPC classification number: G06F13/382 ,  G06F13/4282 ,  H02J7/0047 ,  H02J7/00032 ,  G06F2213/0042

Abstract: Embodiments herein relate to an electronic device that includes a system-on-chip (SoC). The electronic device may further include a USB port to provide a first identification signal that is at a first voltage and that is related to a charging process between a USB device to which the USB port is coupled an the electronic device. The electronic device may further include a power delivery (PD) controller to: generate, based on the first identification signal, a second identification signal at a second voltage that is lower than the first voltage; and provide the second identification signal to the SoC. Other embodiments may be described and claimed.

公开(公告)号：US20220217099A1

公开(公告)日：2022-07-07

申请号：US17704666

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Kar Leong Wong ,  Satheesh Chellappan

IPC: H04L49/109

Abstract: Techniques are provided for on-chip communication. A system implementing the techniques according to an embodiment includes a first virtual physical (vPhy) circuit couplable to a host through a vPhy interface and a second vPhy circuit couplable to a device, on the same chip as the host, through another vPhy interface. The system further includes a vPhy-to-vPhy interface between the vPhy circuits which includes signal lines to transmit a first data toggle signal from the first vPhy circuit to the second vPhy circuit, and a second data toggle signal from the second vPhy circuit to the first vPhy circuit. The first vPhy circuit is configured to generate the first data toggle signal based on a signal received from the host for transmission to the device. The second vPhy circuit is configured to generate the second data toggle signal based on signal received from the device for transmission to the host.

公开(公告)号：US20210266610A1

公开(公告)日：2021-08-26

申请号：US17091865

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Kishore Kasichainula ,  Frank Baehren

IPC: H04N21/233 ,  G06F9/30 ,  H04L29/06

Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.

公开(公告)号：US10834434B2

公开(公告)日：2020-11-10

申请号：US16235934

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Kishore Kasichainula ,  Frank Baehren

IPC: G06F17/00 ,  H04N21/233 ,  G06F9/30 ,  H04L29/06

Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.

公开(公告)号：US20180181371A1

公开(公告)日：2018-06-28

申请号：US15391911

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Hardik Shah

IPC: G06F5/06 ,  H04L29/08 ,  H04L12/879 ,  H04L12/26 ,  G06F5/14

CPC classification number: G06F5/065 ,  G06F5/14 ,  G06F2205/067 ,  G06F2205/126 ,  H04L43/50 ,  H04L49/901 ,  H04L67/141

Abstract: In one embodiment, an apparatus comprises an input output controller. The input output controller is configured to establish a connection between a host computing device and an external device. The input output controller is further configured to determine that the external device is operating using a slower data transmission speed than the input output controller. The input output controller is further configured to throttle data received from the external device.

公开(公告)号：US20180004685A1

公开(公告)日：2018-01-04

申请号：US15196832

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Suketu U. Bhatt ,  Lakshminarayana Pappu ,  Satheesh Chellappan

IPC: G06F13/10 ,  G06F13/42 ,  G06F13/20 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F13/20 ,  G06F13/4027 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0042

Abstract: Described is a host interface, a device interface, a downstream translation circuitry, an upstream translation circuitry, and a host line-state state machine. The host interface may comprise a host line-state output. The device interface may comprise a device line-state output. The downstream translation circuitry may be operable to process a transaction received on the host interface and to generate a transaction for the device interface. The upstream translation circuitry may be operable to process a transaction received on the device interface and to generate a transaction for the host interface. The host line-state state machine may be operable to set the host line-state output to a value that is one of: an SE0-state value, a J-state value, or a K-state value.

公开(公告)号：US11792446B2

公开(公告)日：2023-10-17

申请号：US17091865

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Kishore Kasichainula ,  Frank Baehren

IPC: G06F17/00 ,  H04N21/233 ,  G06F9/30 ,  H04L65/80 ,  H04L65/75

CPC classification number: H04N21/233 ,  G06F9/30003 ,  H04L65/75 ,  H04L65/80

Abstract: Example methods, apparatus, systems and articles of manufacture to reduce audio streaming latency between audio and Gigabit Ethernet subsystems are disclosed herein. An example integrated circuit disclosed herein to process an audio stream associated with an endpoint device on a network includes an Ethernet subsystem to access the network and an audio subsystem to process audio data associated with the audio stream. The disclosed example integrated circuit also includes a direct hardware path between the Ethernet subsystem and the audio subsystem to exchange audio data between the Ethernet subsystem and the audio subsystem without the audio data being processed by a first software driver that is to provide access to the Ethernet subsystem or a second software driver that is to provide access to the audio subsystem.

公开(公告)号：US20220164130A1

公开(公告)日：2022-05-26

申请号：US17666914

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Satheesh Chellappan ,  Tomasz Pielaszkiewicz ,  Devon Worrell

IPC: G06F3/06

Abstract: A system, article, and method of standards-based audio function processing has reduced memory usage by using an address mapping table.

公开(公告)号：US10705142B2

公开(公告)日：2020-07-07

申请号：US15394666

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Suketu U. Bhatt ,  Satheesh Chellappan

IPC: G01R31/00 ,  G01R31/317 ,  G06F11/00

Abstract: Techniques and mechanisms for providing on-chip link control functionality to facilitate emulation of a communication. In an embodiment, an integrated circuit (IC) chip includes a physical layer (PHY) which supports communication compatible with a high-speed serial interface standard. A link controller of the IC chip is coupled between the PHY and an interconnect architecture which variously couples a host and other resources of the IC chip to each other. A test controller of the IC chip signals a test mode to implement a loopback path of the link controller in lieu of one or more functional paths for communication with the PHY. In another embodiment, signal output by the loopback path emulate a communication from a resource other than the test controller.

公开(公告)号：US09904650B2

公开(公告)日：2018-02-27

申请号：US14678712

申请日：2015-04-03

Applicant: Intel Corporation

Inventor： Karthi R. Vadivelu ,  Sridharan Ranganathan ,  Anoop Mukker ,  Satheesh Chellappan

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/12

CPC classification number: G06F13/426 ,  G06F13/122 ,  G06F13/126 ,  G06F13/387 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.