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    Flip-flop circuit with low-leakage transistors
    16.
    发明授权
    Flip-flop circuit with low-leakage transistors 有权

    公开(公告)号：US10423203B2

    公开(公告)日：2019-09-24

    申请号：US15392559

    申请日：2016-12-28

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Rafael Rios ,  Somnath Paul ,  Muhammad M. Khellah

    IPC: G06F1/26 ,  H03K3/012 ,  G06F1/3293 ,  H03K3/356

    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

    PRE-SYNAPTIC LEARNING USING DELAYED CAUSAL UPDATES
    17.
    发明申请
    PRE-SYNAPTIC LEARNING USING DELAYED CAUSAL UPDATES 审中-公开

    公开(公告)号：US20180107922A1

    公开(公告)日：2018-04-19

    申请号：US15294666

    申请日：2016-10-14

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Muhammad M. Khellah

    IPC: G06N3/08 ,  G06N99/00

    Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.

    Concurrent compute and ECC for in-memory matrix vector operations
    19.
    发明授权
    Concurrent compute and ECC for in-memory matrix vector operations 有权

    公开(公告)号：US11513893B2

    公开(公告)日：2022-11-29

    申请号：US17128414

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Chen Koren ,  George Shchupak ,  Muhammad M. Khellah

    IPC: G06F11/00 ,  G06F11/10 ,  G06N3/08

    Abstract: A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.

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