公开(公告)号：US20230137877A1

公开(公告)日：2023-05-04

申请号：US17517152

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Omkar KARHADE ,  Malavarayan SANKARASUBRAMANIAN ,  Dingying XU ,  Gang DUAN ,  Bai NIE ,  Xiaoying GUO ,  Kristof DARMAWIKARTA ,  Hongxia FENG ,  Srinivas PIETAMBARAM ,  Jeremy D. ECTON

IPC: H01L23/00 ,  H01L25/065

Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

公开(公告)号：US20210082852A1

公开(公告)日：2021-03-18

申请号：US16572354

申请日：2019-09-16

Applicant: Intel Corporation

Inventor： Bradon C. MARIN ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Jacob VEHONSKY

IPC: H01L23/00 ,  C25D3/38 ,  C25D7/12 ,  C25D5/02

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

公开(公告)号：US20200006232A1

公开(公告)日：2020-01-02

申请号：US16024707

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20240188225A1

公开(公告)日：2024-06-06

申请号：US18060598

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Rengarajan SHANMUGAM ,  Srinivas PIETAMBARAM ,  Mao-Feng TSENG ,  Yonggang LI

IPC: H05K3/40 ,  C23C18/18 ,  C23C18/38 ,  H05K1/03 ,  H05K1/11 ,  H05K3/18

CPC classification number: H05K3/4038 ,  C23C18/1868 ,  C23C18/38 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/181 ,  H05K2201/09563 ,  H05K2201/2081 ,  H05K2203/107

Abstract: A method for manufacturing a structured substrate is provided, the method including: forming a plurality of openings extending from a first surface of a substrate towards a second surface of the substrate, wherein the first surface is coplanar to the second surface, wherein the substrate comprises glass, and wherein each of the openings comprises a sidewall; forming a first layer at least on the sidewall of the openings; forming a second layer on the first layer, wherein the second layer comprises titanium; and depositing metal on the second layer to at least partially fill the openings.

公开(公告)号：US20240188222A1

公开(公告)日：2024-06-06

申请号：US18060595

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Darko GRUJICIC ,  Marcel WALL ,  Jason STEILL

IPC: H05K3/22 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/225 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/002 ,  H05K3/0029 ,  H01L21/486

Abstract: The present disclosure is directed to a method providing a substrate core having a glass core layer with top and bottom surfaces and a build-up process performing operations to form a plurality of through-glass vias formed through the glass core layer and a plurality of conductive layers on the top and bottom surfaces of the glass core layer. As an integral part of the build-up process, a defect detection method may be used to detect defects in the glass core layer. The inspection for defects may be performed after selected operations. After one or more defect (e.g., crack) is uncovered, a repair process may be performed to repair the defects in the glass core layer. The repair of a defect may be performed immediately upon detection or after selected operations as a comprehensive repair of a group of defects.

公开(公告)号：US20230361044A1

公开(公告)日：2023-11-09

申请号：US18224794

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Rahul MANEPALLI ,  Gang DUAN

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5381 ,  H01L23/5386 ,  H01L23/3107 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/6835 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/5384 ,  H01L2225/06589 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06582

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20230361002A1

公开(公告)日：2023-11-09

申请号：US17738085

申请日：2022-05-06

Applicant: Intel Corporation

Inventor： Vinith BEJUGAM ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Samuel GEORGE ,  Srinivas PIETAMBARAM

IPC: H01L23/48 ,  H01L23/15 ,  H01L21/48 ,  H01L21/68

CPC classification number: H01L23/481 ,  H01L23/15 ,  H01L21/486 ,  H01L21/68

Abstract: The present disclosure is directed to semiconductor dies and methods that provide a glass substrate, a pulsed laser tool to produce a line-shaped modification to the glass substrate for forming a plurality of structures in the glass substrate. The pulse laser tool may be provided with a predetermined pattern for its movement. The predetermined pattern moves the pulsed laser tool in a series of single steps in a first axial direction and in a series of plural lateral steps in a second axial direction that is perpendicular to the first axial direction, in particular, the single step is followed by the plural lateral steps in a repeating sequence. The series of plural lateral steps form an assembly of line-shaped modifications in parallel rows on the glass substrate, and thereafter the plurality of structures may be formed from the parallel rows of line-shaped modifications in the glass substrate.

公开(公告)号：US20230343774A1

公开(公告)日：2023-10-26

申请号：US18216275

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI

IPC: H01L23/538 ,  H01L23/29 ,  H01L21/683 ,  H01L25/00 ,  H01L23/48 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5389 ,  H01L2221/68309 ,  H01L2221/68345 ,  H01L2221/68359

Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

公开(公告)号：US20220115367A1

公开(公告)日：2022-04-14

申请号：US17556660

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI

IPC: H01L25/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/29 ,  H01L21/683 ,  H01L23/31

Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

公开(公告)号：US20210028080A1

公开(公告)日：2021-01-28

申请号：US16522494

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert L. Sankman ,  Rahul Manepalli ,  Gang Duan ,  Debendra Mallik

IPC: H01L23/15 ,  H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/495

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.