公开(公告)号：US20250107112A1

公开(公告)日：2025-03-27

申请号：US18371294

申请日：2023-09-21

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Srinivas PIETAMBARAM ,  Mohammad Mamunur RAHMAN ,  Sashi Shekhar KANDANUR ,  Aleksandar ALEKSOV ,  Tarek A. IBRAHIM ,  Rahul N. MANEPALLI

IPC: H01L23/48 ,  H01L23/498

Abstract: Coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. The coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. Methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.

公开(公告)号：US20240243088A1

公开(公告)日：2024-07-18

申请号：US18622486

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Rahul MANEPALLI ,  Srinivas PIETAMBARAM ,  Jacob VEHONSKY

IPC: H01L23/00 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12

CPC classification number: H01L24/14 ,  C25D3/38 ,  C25D5/022 ,  C25D7/12 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/1403

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to manufacturing a package having a substrate with a first side and a second side opposite the first side, where a copper layer is coupled with a first region of the first side of the substrate and includes a plurality of bumps coupled with the first region of the first side of the substrate where one or more second regions on the first side of the substrate not coupled with a copper layer, and where a layout of the one or more second regions on the first side of the substrate is to vary a growth, respectively, of each of the plurality of bumps during a plating process by modifying a local copper density of each of the plurality of bumps.

公开(公告)号：US20240088121A1

公开(公告)日：2024-03-14

申请号：US18511641

申请日：2023-11-16

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Rahul N. MANEPALLI ,  Sri Ranga Sai BOYAPATI

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US20230134049A1

公开(公告)日：2023-05-04

申请号：US18089227

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20230015619A1

公开(公告)日：2023-01-19

申请号：US17952080

申请日：2022-09-23

Applicant: Intel Corporation

Inventor： Kristof DARMAWAIKARTA ,  Robert MAY ,  Sashi KANDANUR ,  Sri Ranga Sai BOYAPATI ,  Srinivas PIETAMBARAM ,  Steve CHO ,  Jung Kyu HAN ,  Thomas HEATON ,  Ali LEHAF ,  Ravindranadh ELURI ,  Hiroki TANAKA ,  Aleksandar ALEKSOV ,  Dilan SENEVIRATNE

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US20200266184A1

公开(公告)日：2020-08-20

申请号：US16649923

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Robert Alan MAY ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Rahul N. MANEPALLI ,  Sri Ranga Sai BOYAPATI

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US20240282591A1

公开(公告)日：2024-08-22

申请号：US18171683

申请日：2023-02-21

Applicant: Intel Corporation

Inventor： Oladeji FADAYOMI ,  Shaojiang CHEN ,  Jeremy ECTON ,  Matthew TINGEY ,  Srinivas PIETAMBARAM ,  Leonel ARANA

IPC: H01L21/48 ,  C23F1/02

CPC classification number: H01L21/486 ,  C23F1/02

Abstract: The present disclosure is directed to a planarization tool having at least one module with a target holder for supporting a target with a metal layer, at least one of a plurality of etch inhibitor dispensers for discharging an etch inhibitor toward the target, and a plurality of nozzles for discharging a chemical etchant at an angle towards the target to perform selective removal of the metal layer for planarization of the target. In an aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be combined as a single unit to discharge the chemical etchant and the etch inhibitor together. In another aspect, the plurality of etch inhibitor dispensers and the plurality of nozzles may be configured in a single module or separate modules.

公开(公告)号：US20240250043A1

公开(公告)日：2024-07-25

申请号：US18606876

申请日：2024-03-15

Applicant: Intel Corporation

Inventor： Srinivas PIETAMBARAM ,  Gang DUAN ,  Deepak KULKARNI ,  Rahul MANEPALLI ,  Xiaoying GUO

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.

公开(公告)号：US20240177907A1

公开(公告)日：2024-05-30

申请号：US18059992

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Yosef KORNBLUTH ,  Whitney BRYKS ,  Ravindranadh ELURI ,  Aaditya Anand CANDADAI ,  Srinivas PIETAMBARAM

IPC: H01F7/20 ,  B32B3/18

CPC classification number: H01F7/206 ,  B32B3/18 ,  B32B15/18

Abstract: The present disclosure is directed to a carrier chuck having a base plate with a top surface, a plurality of first magnets positioned in a first region of the top surface, the plurality of first magnets configured to produce a first electromagnetic field to retain or suspend a panel placed on the carrier chuck during panel processing, wherein the first region corresponds to a region of the panel which comprises a magnetic material.

公开(公告)号：US20240128205A1

公开(公告)日：2024-04-18

申请号：US18397915

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.