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    DEVICE, SYSTEM, AND METHOD TO CHANGE A CONSISTENCY OF BEHAVIOR BY A CELL CIRCUIT
    13.
    发明申请
    DEVICE, SYSTEM, AND METHOD TO CHANGE A CONSISTENCY OF BEHAVIOR BY A CELL CIRCUIT 审中-公开

    公开(公告)号：US20200312404A1

    公开(公告)日：2020-10-01

    申请号：US16417538

    申请日：2019-05-20

    Applicant: Intel Corporation

    Inventor： Vivek De ,  Sanu Mathew ,  Sudhir Satpathy ,  Vikram Suresh ,  Raghavan Kumar

    IPC: G11C11/419 ,  H04L9/32

    Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

    APPARATUS AND METHOD FOR GENERATING HYBRID STATIC/DYNAMIC ENTROPY PHYSICALLY UNCLONABLE FUNCTION
    15.
    发明申请
    APPARATUS AND METHOD FOR GENERATING HYBRID STATIC/DYNAMIC ENTROPY PHYSICALLY UNCLONABLE FUNCTION 审中-公开

    公开(公告)号：US20190305970A1

    公开(公告)日：2019-10-03

    申请号：US15942181

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

    IPC: H04L9/32 ,  H04L9/00

    Abstract: An apparatus is provided which comprises: an entropy source to produce a first random sequence of bits, wherein the entropy source comprises an array of bi-stable cross-coupled inverter cells; a first circuitry coupled to the entropy source, wherein the first circuitry to generate an entropy source selection set; and a second circuitry coupled to the entropy source and the first circuitry, wherein the second circuitry is to receive the first random sequence and the entropy source selection set, and wherein the second circuitry is to generate a second random sequence.

    Hybrid AES-SMS4 hardware accelerator
    17.
    发明授权
    Hybrid AES-SMS4 hardware accelerator 有权

    公开(公告)号：US10218497B2

    公开(公告)日：2019-02-26

    申请号：US15252741

    申请日：2016-08-31

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

    IPC: G06F9/30 ,  G09C1/00 ,  H04L9/06

    Abstract: A hybrid AES-SMS4 hardware accelerator is described. A System on Chip implementing a hybrid AES-SMS4 hardware accelerator may include a processor core and a single hardware accelerator coupled to the processor core, the single hardware accelerator to encrypt or decrypt data. The single hardware accelerator may include a first block cipher to encrypt or decrypt the data according to a first encryption algorithm and a second block cipher to encrypt or decrypt the data according to a second encryption algorithm. The accelerator may further include a combined substitution box (Sbox) coupled to the first block cipher and the second block cipher, the combined Sbox comprising logic to perform Galois Field (GF) multiplications and inverse computations, wherein the inverse computations are common to the first block cipher and the second block cipher.

    Unified AES-SMS4—Camellia symmetric key block cipher acceleration
    18.
    发明授权
    Unified AES-SMS4—Camellia symmetric key block cipher acceleration 有权

    公开(公告)号：US11121856B2

    公开(公告)日：2021-09-14

    申请号：US16010206

    申请日：2018-06-15

    Applicant: Intel Corporation

    Inventor： Sudhir Satpathy ,  Vikram Suresh ,  Sanu Mathew

    IPC: H04L9/06 ,  G09C1/00 ,  G06F7/72

    Abstract: Disclosed embodiments relate to a unified Advanced Encryption Standard (AES), SMS4, and Camellia (CML) accelerator. In one example, a processor includes fetch circuitry to fetch a cipher instruction specifying an opcode, a datum, and a key, the opcode to specify one of three cryptographic modes and an operation, decode circuitry to decode the fetched cipher instruction, and execution circuitry to respond to the decoded cipher instruction by performing the operation using a selected one of three block ciphers corresponding to the specified cryptographic mode and a unified cipher datapath shared by the three block ciphers, the unified cipher datapath comprising a plurality of hybrid substitution boxes (Sboxes) to perform Galois Field (GF) multiplications and inverse computations, wherein the unified cipher datapath is to implement an eighth-order polynomial isomorphically equivalent to each polynomial used by the three block ciphers by calculating and then combining two fourth-order polynomials.

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