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    Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator
    1.
    发明授权
    Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator 有权

    公开(公告)号：US10928847B2

    公开(公告)日：2021-02-23

    申请号：US16147652

    申请日：2018-09-29

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Sudhir Satpathy

    IPC: G06F9/02 ,  G06F1/06

    Abstract: Methods and apparatuses relating to a hashing accelerator having a frequency scaled message scheduler data path circuit are described. In one embodiment, a hardware accelerator includes a message digest data path circuit comprising a first message digest circuit to output a second state vector, at a first clock rate, based on a first state vector and an output from a first switch, and a second message digest circuit to output a third state vector, at the first clock rate, based on the second state vector and an output from a second switch; a message scheduler data path circuit comprising at least one first message scheduler circuit to output an element into a second message vector, at a second clock rate that is slower than the first clock rate, based on a plurality of elements of a first message vector, and at least one second message scheduler circuit to output an element into a fourth message vector, at the second clock rate that is slower than the first clock rate, based on a plurality of elements of a third message vector; and a controller to switch the first switch at the second clock rate between sourcing a first element of the first message vector and a first element of the third message vector as the output from the first switch, and switch the second switch at the second clock rate between sourcing a second element of the first message vector and a second element of the third message vector as the output from the second switch.

    Hardware accelerators and methods for high-performance authenticated encryption
    2.
    发明授权
    Hardware accelerators and methods for high-performance authenticated encryption 有权

    公开(公告)号：US10705842B2

    公开(公告)日：2020-07-07

    申请号：US15943654

    申请日：2018-04-02

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sanu Mathew ,  Sudhir Satpathy ,  Vinodh Gopal

    IPC: G06F9/302 ,  G06F9/305 ,  G06F9/315 ,  H04L9/00 ,  H04L9/18 ,  G06F9/30 ,  G06F9/38 ,  H04L9/06

    Abstract: Methods and apparatuses relating to high-performance authenticated encryption are described. A hardware accelerator may include a vector register to store an input vector of a round of an encryption operation; a circuit including a first data path including a first modular adder coupled to a first input from the vector register and a second input from the vector register, and a second modular adder coupled to the first modular adder and a second data path from the vector register, and the second data path including a first logical XOR circuit coupled to the second input and a third data path from the vector register, a first rotate circuit coupled to the first logical XOR circuit, a second logical XOR circuit coupled to the first rotate circuit and the third data path, and a second rotate circuit coupled to the second logical XOR circuit; and a control circuit to cause the first modular adder and the second modular adder of the first data path and the first logical XOR circuit, the second logical XOR circuit, the first rotate circuit, and the second rotate circuit of the second data path to perform a portion of the round according to one or more control values, and store a first result from the first data path for the portion and a second result from the second data path for the portion into the vector register.

    Techniques for secure authentication
    3.
    发明授权
    Techniques for secure authentication 有权

    公开(公告)号：US10326596B2

    公开(公告)日：2019-06-18

    申请号：US15283315

    申请日：2016-10-01

    Applicant: INTEL CORPORATION

    Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

    IPC: H04L9/00 ,  H04L9/32 ,  H04L9/06 ,  G06F7/72 ,  G09C1/00 ,  H04L9/28

    Abstract: Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.

    Device, system, and method to change a consistency of behavior by a cell circuit
    4.
    发明授权
    Device, system, and method to change a consistency of behavior by a cell circuit 有权

    公开(公告)号：US10825511B2

    公开(公告)日：2020-11-03

    申请号：US16417538

    申请日：2019-05-20

    Applicant: Intel Corporation

    Inventor： Vivek De ,  Sanu Mathew ,  Sudhir Satpathy ,  Vikram Suresh ,  Raghavan Kumar

    IPC: G11C11/419 ,  H04L9/32 ,  G09G5/00 ,  G06F7/58

    Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

    Bitcoin mining hardware accelerator with optimized message digest and message scheduler datapath
    5.
    发明授权
    Bitcoin mining hardware accelerator with optimized message digest and message scheduler datapath 有权

    公开(公告)号：US10755242B2

    公开(公告)日：2020-08-25

    申请号：US15274200

    申请日：2016-09-23

    Applicant: Intel Corporation

    Inventor： Vikram Suresh ,  Sudhir Satpathy ,  Sanu Mathew

    IPC: G06Q20/06 ,  G09C1/00 ,  G06Q20/02 ,  H04L9/06 ,  G06F9/48 ,  G06Q20/38

    Abstract: A Bitcoin mining hardware accelerator is described. A System on Chip implementing a Bitcoin mining hardware accelerator may include a processor core and a hardware accelerator coupled to the processor core, the hardware accelerator to mine digital currency. The hardware accelerator may include a first computational block, including a message digest datapath, wherein the first computational block is to: precompute a first summation of a 32-bit message (Wi), a 32-bit round constant (Ki), and a content of a first shifted state register (Gi−1), and store a result of the first summation in a state register (Hi). The Bitcoin mining hardware accelerator may further include a second computational block comprising a message scheduler datapath.

    SMS4 acceleration hardware
    7.
    发明授权
    SMS4 acceleration hardware 有权
    SMS4加速硬件

    公开(公告)号：US09503256B2

    公开(公告)日：2016-11-22

    申请号：US14582707

    申请日：2014-12-24

    Applicant: Intel Corporation

    Inventor： Kirk Yap ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

    IPC: H04L9/00 ,  H04L9/08 ,  H04L9/14

    CPC classification number: H04L9/0822 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

    Abstract: Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

    Abstract translation: 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮密钥扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

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