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公开(公告)号:US12182570B2
公开(公告)日:2024-12-31
申请号:US17359354
申请日:2021-06-25
Applicant: Intel Corporation
Inventor: Deepti Aggarwal , Michael Espig , Robert Valentine , Sumit Mohan , Prakaram Joshi , Richard Winterton
IPC: G06F9/30
Abstract: Systems, methods, and apparatuses to support packed data convolution instructions with shift control and width control are described. In one embodiment, a hardware processor includes a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction having fields that identify a first packed data source, a second packed data source, a packed data destination, a sliding window width, and a stride, and an opcode that indicates an execution circuit is to generate a first chunk of contiguous elements of the first packed data source having a width of the sliding window width, generate a second chunk of contiguous elements of the first packed data source having the width of the sliding window width and shifted by the stride, multiply each element of the first chunk by a corresponding element of a respective chunk of the second packed data source to generate a first set of products, add the first set of products together to generate a first sum, multiply each element of the second chunk by a corresponding element of a respective chunk of the second packed data source to generate a second set of products, add the second set of products together to generate a second sum, and store the first sum in a first element of the packed data destination and the second sum in a second element of the packed data destination; and the execution circuit is to execute the decoded single instruction according to the opcode.
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公开(公告)号:US20210374896A1
公开(公告)日:2021-12-02
申请号:US17159708
申请日:2021-01-27
Applicant: Intel Corporation
Inventor: Abhishek R. Appu , Stanley J. Baran , Sang-Hee Lee , Atthar H. Mohammed , Jong Dae Oh , Hiu-Fai R. Chan , Jill M. Boyce , Fangwen Fu , Satya N. Yedidi , Sumit Mohan , James M. Holland , Keith W. Rowe , Altug Koker
IPC: G06T1/20 , G06T1/60 , G09G5/00 , H04N19/156 , G06F1/3206 , G06F1/3234
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a power budget analyzer to identify a power budget for one or more of the application processor, the persistent storage media, and the graphics subsystem, a target analyzer communicatively coupled to the graphics subsystem to identify a target for the graphics subsystem, and a parameter adjuster to adjust one or more parameters of the graphics subsystem based on one or more of the identified power budget and the identified target.
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13.
公开(公告)号:US11051038B2
公开(公告)日:2021-06-29
申请号:US16707485
申请日:2019-12-09
Applicant: Intel Corporation
Inventor: Jill M. Boyce , Sumit Mohan , James M. Holland , Sang-Hee Lee , Abhishek R. Appu , Wen-Fu Kao , Joydeep Ray , Ya-Ti Peng , Keith W. Rowe , Fangwen Fu , Satya N. Yedidi
IPC: H04N19/593 , H04N19/597 , G06T11/00 , H04N19/52 , H04N19/176 , H04N19/105 , H04N19/436 , H04N19/46 , H04N19/136
Abstract: An embodiment of an electronic processing system may include a 2D frame which corresponds to a projection of a 360 video space, and a component predictor to predict an encode component for a first block of a 2D frame based on encode information from a neighboring block which is neighboring to the first block of the 2D frame only in the 360 video space, a prioritizer to prioritize transmission for a second block of the 2D frame based on an identified region of interest, and/or a format detector to detect a 360 video format of the 2D frame based on image content. A 360 video capture device may include a contextual tagger to tag 360 video content with contextual information which is contemporaneous with the captured 360 video content. Other embodiments are disclosed and claimed.
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公开(公告)号:US10908679B2
公开(公告)日:2021-02-02
申请号:US15495034
申请日:2017-04-24
Applicant: Intel Corporation
Inventor: Robert J. Johnston , Satyanarayana Avadhanam , Changliang Wang , Narayan Biswal , Archie Sharma , Richmond Hicks , Joydeep Ray , Abhishek R. Appu , Stanley J. Baran , Sang-Hee Lee , Atthar H. Mohammed , Jong Dae Oh , Hiu-Fai Chan , Sumit Mohan , Jill M. Boyce , Yi-Jen Chiu
Abstract: Systems, apparatuses and methods may provide for technology to improve user experience when viewing simulated 3D objects on a display. Head and upper-body movements may be tracked and recognized as gestures to alter the displayed viewing angle. The technology provides for a very natural way to look around, under, or over objects.
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公开(公告)号:US20200304710A1
公开(公告)日:2020-09-24
申请号:US16808626
申请日:2020-03-04
Applicant: Intel Corporation
Inventor: Jill M. Boyce , Stanley J. Baran , Sumit Mohan , Yi-Jen Chiu , Jason Tanner , Atthar H. Mohammed , Richmond Hicks , Barnan Das
IPC: H04N5/232 , H04N5/247 , H04N7/18 , H04N21/6587 , H04N21/84 , H04N21/4728 , H04N21/218 , H04N21/81 , H04L29/06
Abstract: Systems, apparatuses and methods may determine, on a per camera basis, an interest level with respect to panoramic video content, identify a subset of cameras in a plurality of cameras for which the interest level is below a threshold, and reduce power consumption in the subset of cameras. Additionally, technology may determine a projection format associated with panoramic video content, identify one or more discontinuous boundaries in the projection format, and modify an encoding scheme associated with the panoramic video content based on the discontinuous boundaries. Moreover, an encoded frame may be assigned to a temporal scalability layer that has a higher priority than a layer to which an asynchronous space warp frame is assigned. Additionally, technology may reduce the encoding complexity of a boundary between an active region and an inactive region in fisheye content.
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公开(公告)号:US10666946B2
公开(公告)日:2020-05-26
申请号:US15282508
申请日:2016-09-30
Applicant: Intel Corporation
Inventor: Sean J. Lawrence , Frederic J. Noraz , Jill M. Boyce , Sumit Mohan
IPC: H04N19/139 , H04N19/105 , H04N19/172 , H04N19/176 , H04N19/182 , H04N19/162 , H04N19/51 , H04N19/17 , H04N19/164 , H04N19/20
Abstract: Techniques described herein are related to video coding using display modification input.
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17.
公开(公告)号:US20200092185A1
公开(公告)日:2020-03-19
申请号:US16682291
申请日:2019-11-13
Applicant: Intel Corporation
Inventor: Eugene Yasman , Nir Gerber , Sumit Mohan , Jean-Pierre Giacalone
IPC: H04L12/26 , H04L12/861 , H04L12/883
Abstract: Technologies for low-latency data streaming include a computing device having a processor that includes a producer and a consumer. The producer generates a data item, and in a local buffer producer mode adds the data item to a local buffer, and in a remote buffer producer mode adds the data item to a remote buffer. When the local buffer is full, the producer switches to the remote buffer producer mode, and when the remote buffer is below a predetermined low threshold, the producer switches to the local buffer producer mode. The consumer reads the data item from the local buffer while operating in a local buffer consumer mode and reads the data item from the remote buffer while operating in a remote buffer consumer mode. When the local buffer is above a predetermined high threshold, the consumer may switch to a catch-up operating mode. Other embodiments are described and claimed.
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公开(公告)号:US10424082B2
公开(公告)日:2019-09-24
申请号:US15495238
申请日:2017-04-24
Applicant: Intel Corporation
Inventor: Jill M. Boyce , Keith W. Rowe , James M. Holland , Fangwen Fu , Satya N. Yedidi , Sumit Mohan
Abstract: A system includes a camera to capture real world content and a semiconductor package apparatus. The semiconductor package apparatus includes a substrate and logic. The logic includes a graphics pipeline to generate rendered content, a base layer encoder to encode real world content into a base layer and a first layer encoder to encode rendered content into a first non-base layer, a multiplexer to interleave the base layer with the first non-base layer to obtain a single output signal having mixed reality content, and a transmitter to transmit the single output signal. The system further includes a second layer encoder to encode map data into a second non-base layer. The multiplexer to interleave the second non-base layer with the first non-base layer and the base layer. The first and second layer encoders encode the rendered content and the map data into overlay auxiliary pictures.
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公开(公告)号:US20180295282A1
公开(公告)日:2018-10-11
申请号:US15483787
申请日:2017-04-10
Applicant: Intel Corporation
Inventor: Jill M. Boyce , Stanley J. Baran , Sumit Mohan , Yi-Jen Chiu , Jason Tanner , Atthar H. Mohammed , Richmond Hicks , Barnan Das
Abstract: Systems, apparatuses and methods may determine, on a per camera basis, an interest level with respect to panoramic video content, identify a subset of cameras in a plurality of cameras for which the interest level is below a threshold, and reduce power consumption in the subset of cameras. Additionally, technology may determine a projection format associated with panoramic video content, identify one or more discontinuous boundaries in the projection format, and modify an encoding scheme associated with the panoramic video content based on the discontinuous boundaries. Moreover, an encoded frame may be assigned to a temporal scalability layer that has a higher priority than a layer to which an asynchronous space warp frame is assigned. Additionally, technology may reduce the encoding complexity of a boundary between an active region and an inactive region in fisheye content.
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公开(公告)号:US12101475B2
公开(公告)日:2024-09-24
申请号:US17127544
申请日:2020-12-18
Applicant: Intel Corporation
Inventor: Brinda Ganesh , Nilesh Jain , Sumit Mohan , Faouzi Kossentini , Jill Boyce , James Holland , Zhijun Lei , Chekib Nouira , Foued Ben Amara , Hassene Tmar , Sebastian Possos , Craig Hurst
IPC: H04N19/114 , H04N19/154
CPC classification number: H04N19/114 , H04N19/154
Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.
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