公开(公告)号：US11837542B2

公开(公告)日：2023-12-05

申请号：US17583078

申请日：2022-01-24

Applicant: INTEL CORPORATION

Inventor： Manish Chandhok ,  Richard Schenker ,  Tristan Tronic

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76846 ,  H01L23/53223 ,  H01L23/53266

Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.

公开(公告)号：US20220139823A1

公开(公告)日：2022-05-05

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11264325B2

公开(公告)日：2022-03-01

申请号：US16628991

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Manish Chandhok ,  Richard Schenker ,  Tristan Tronic

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: Integrated circuit (IC) structures, computing devices, and related methods are disclosed. An IC structure includes an interlayer dielectric (ILD), an interconnect, and a liner material separating the interconnect from the ILD. The interconnect includes a first end extending to or into the ILD and a second end opposite the first end. A second portion of the interconnect extending from the second end to a first portion of the interconnect proximate to the first end does not include the liner material thereon. A method of manufacturing an IC structure includes removing an ILD from between interconnects, applying a conformal hermetic liner, applying a carbon hard mask (CHM) between the interconnects, removing a portion of the CHM, removing the conformal hermetic liner to a remaining CHM, and removing the exposed portion of the liner material to the remaining CHM to expose the second portion of the interconnects.

公开(公告)号：US20250112155A1

公开(公告)日：2025-04-03

申请号：US18374532

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Scott Clendenning ,  Feras Eid ,  Robert Jordan ,  Wenhao Li ,  Jiun-Ruey Chen ,  Tayseer Mahdi ,  Carlos Felipe Bedoya Arroyave ,  Shashi Bhushan Sinha ,  Anandi Roy ,  Tristan Tronic ,  Dominique Adams ,  William Brezinski ,  Richard Vreeland ,  Thomas Sounart ,  Brian Barley ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/48 ,  H01L23/498 ,  H01L23/528

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.

公开(公告)号：US20250006433A1

公开(公告)日：2025-01-02

申请号：US18216479

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Sarah Atanasov ,  Elijah Karpov ,  Nazila Haratipour ,  Sou-Chi Chang ,  Tristan Tronic

IPC: H01G7/06 ,  H10B53/00

Abstract: Apparatuses, memory systems, capacitor structures, and techniques related to ferroelectric capacitors having a hafnium-zirconium oxide film between the electrodes of the capacitor are discussed. The hafnium-zirconium oxide film is thin and has large crystallite grains. The thin large grain hafnium-zirconium oxide film having large grains is formed by depositing a thick hafnium-zirconium oxide film and annealing the thick hafnium-zirconium oxide film to establish the large grain size, and etching back the hafnium-zirconium oxide film to the desired thickness for deployment in the ferroelectric capacitor.

公开(公告)号：US11769814B2

公开(公告)日：2023-09-26

申请号：US16455659

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Kevin L. Lin ,  Tristan Tronic

IPC: H01L29/51 ,  H01L29/66

CPC classification number: H01L29/515 ,  H01L29/6653

Abstract: A device is disclosed. The device includes a gate conductor, a first source-drain region and a second source-drain region. The device includes a first air gap space between the first source-drain region and a first side of the gate conductor and a second air gap space between the second source-drain region and a second side of the gate conductor. A hard mask layer that includes holes is under the gate conductor, the first source-drain region, the second source-drain region and the air gap spaces. A planar dielectric layer is under the hard mask.

公开(公告)号：US20220352068A1

公开(公告)日：2022-11-03

申请号：US17841551

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11444024B2

公开(公告)日：2022-09-13

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.