公开(公告)号：US20220406523A1

公开(公告)日：2022-12-22

申请号：US17350164

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Aleksandar ALEKSOV ,  Georgios C. DOGIAMIS ,  Hiroki TANAKA

IPC: H01G4/002

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to creating capacitors at the interface of a glass substrate. These capacitors may be three-dimensional (3-D) capacitors formed using trenches within the glass core of the substrate using laser-assisted etching techniques. A first electrode may be formed on the glass, including on the surface of trenches or other features etched in the glass, followed by a deposition of a dielectric material or a capacitive material. A second electrode may then be formed on top of the dielectric material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230208010A1

公开(公告)日：2023-06-29

申请号：US17561733

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV ,  Veronica STRONG ,  Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR ,  Brandon RAWLINGS

IPC: H01Q1/22 ,  H01Q13/10 ,  H01L23/498

CPC classification number: H01Q1/2283 ,  H01Q13/10 ,  H01L23/49822 ,  H05K1/181

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, an electromagnetic wave launcher is embedded in the core. In an embodiment, the electromagnetic wave launcher comprises a fin, where the fin is a conductive material, and where the fin comprises a stepped profile.

公开(公告)号：US20230207493A1

公开(公告)日：2023-06-29

申请号：US17561578

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Aleksandar ALEKSOV ,  Veronica STRONG ,  Neelam PRABHU GAUNKAR ,  Brandon RAWLINGS ,  Gerogios C. DOGIAMIS

IPC: H01L23/64 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/15 ,  H01L23/49827

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a magnetic ring is embedded in the substrate. In an embodiment, a loop is around the magnetic ring. In an embodiment, the loop is conductive and comprises a first via through the substrate, a second via through the substrate, and a trace over a surface of the substrate, where the trace electrically couples the first via to the second via.

公开(公告)号：US20230207408A1

公开(公告)日：2023-06-29

申请号：US17561735

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Neelam PRABHU GAUNKAR ,  Brandon RAWLINGS ,  Veronica STRONG

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L21/486 ,  H01L24/16 ,  C03C23/0025

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core. In an embodiment, the core comprises glass. In an embodiment, a blind via is provided into the core. In an embodiment, a plate spans across the blind via.

公开(公告)号：US20230207407A1

公开(公告)日：2023-06-29

申请号：US17561734

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Brandon RAWLINGS ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Aleksandar ALEKSOV

IPC: H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L21/486 ,  H01L24/16 ,  C03C23/0025

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a via opening is formed through the core. In an embodiment, the via opening has an aspect ratio (depth:width) that is approximately 5:1 or greater. In an embodiment, the electronic package further comprises a via in the via opening, where the via opening is fully filled.

公开(公告)号：US20230197541A1

公开(公告)日：2023-06-22

申请号：US17557913

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Telesphor KAMGAING ,  Aleksandar ALEKSOV ,  Georgios C. DOGIAMIS ,  Brandon RAWLINGS ,  Neelam PRABHU GAUNKAR

IPC: H01L23/15 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49816

Abstract: Embodiments disclosed herein include an electronic package that comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass. In an embodiment, the electronic package further comprises an opening through the substrate from the first surface to the second surface, where the opening comprises a first end proximate to the first surface of the substrate, a second end proximate to the second surface of the substrate, and a middle region between the first end and the second end. In an embodiment, the middle region has a discontinuous slope at junctions with the first end and the second end.

公开(公告)号：US20220407203A1

公开(公告)日：2022-12-22

申请号：US17350169

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Veronica STRONG ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR ,  Aleksandar ALEKSOV

IPC: H01P3/06 ,  H01L49/02 ,  H01L23/15 ,  H01L23/498 ,  H01L23/66 ,  H01L21/48 ,  H01P11/00

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to creating coaxial structures within glass package substrates. These techniques, in embodiments, may be extended to create other structures, for example capacitors within glass substrates. Other embodiments may be described and/or claimed.

公开(公告)号：US20220407199A1

公开(公告)日：2022-12-22

申请号：US17354903

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Georgios C. DOGIAMIS ,  Telesphor KAMGAING

IPC: H01P1/20 ,  H05K1/02 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments disclosed herein include package substrates with filter architectures. In an embodiment, a package substrate comprises a core with a first surface and a second surface, and a filter embedded in the core. In an embodiment, the filter comprises a ground plane, where the ground plane is substantially orthogonal to the first surface of the core, and a resonator adjacent to the ground plane.

公开(公告)号：US20220406991A1

公开(公告)日：2022-12-22

申请号：US17349653

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Neelam PRABHU GAUNKAR ,  Telesphor KAMGAING ,  Veronica STRONG ,  Georgios C. DOGIAMIS ,  Aleksandar ALEKSOV

IPC: H01L43/02 ,  H01L23/13 ,  H01L23/15 ,  H01L23/473 ,  H01L23/498 ,  H01L23/66 ,  H01L27/22

Abstract: Embodiments disclosed herein comprise package substrates and methods of forming such package substrates. In an embodiment, a package substrate comprises a core, where the core comprises glass. In an embodiment, an opening if formed through the core. In an embodiment, a magnetic region is disposed in the opening.

公开(公告)号：US20220084931A1

公开(公告)日：2022-03-17

申请号：US17537406

申请日：2021-11-29

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Brandon RAWLINGS ,  Johanna SWAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

Abstract: A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.