公开(公告)号：US08084321B2

公开(公告)日：2011-12-27

申请号：US13151922

申请日：2011-06-02

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: H01L21/8234

CPC classification number: H01L28/87 ,  H01L27/1085

Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

公开(公告)号：US20080057660A1

公开(公告)日：2008-03-06

申请号：US11511977

申请日：2006-08-29

Applicant: Kuo-Chi Tu ,  Jai-Hoon Sim ,  Chun-Yao Chen

Inventor： Kuo-Chi Tu ,  Jai-Hoon Sim ,  Chun-Yao Chen

IPC: H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/10873 ,  H01L27/10885 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/66787 ,  H01L29/7835

Abstract: A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source/drain region located within the recessed region and one source/drain region located out of the recessed region, a storage device connected to the source/drain located out of the recessed region, and a bit line connected to the source/drain located within the recessed region.

Abstract translation: 一种使用凹陷步进栅极的半导体器件。 一个实施例包括在衬底的一部分中的凹陷区域，具有位于凹陷区域内的一个源极/漏极区域和位于凹陷区域外部的一个源极/漏极区域的晶体管，连接到源极/漏极的存储器件 以及连接到位于凹陷区域内的源极/漏极的位线。

公开(公告)号：US06414347B1

公开(公告)日：2002-07-02

申请号：US09790011

申请日：2001-02-09

Applicant: Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

Inventor： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

IPC: H01L2972

CPC classification number: H01L27/10864 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/10841 ,  H01L29/66666 ,  H01L29/7827

Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

Abstract translation: 一种用于制造垂直MOSFET结构的改进方法，包括：一种形成半导体存储单元阵列结构的方法，包括：提供垂直MOSFET DRAM单元结构，其具有平坦化到覆盖硅上的沟槽顶部氧化物的顶表面的沉积栅极导体层 基质; 在所述硅衬底的顶表面下方的所述栅极导体层中形成凹部; 以一定角度注入N型掺杂剂物质通过凹槽形成阵列P-阱中的掺杂凹坑; 将氧化物层沉积到所述凹部中并蚀刻所述氧化物层以在所述凹部的侧壁上形成间隔物; 将栅极导体材料沉积到所述凹部中并将所述栅极导体平坦化到所述沟槽顶部氧化物的所述顶表面。

公开(公告)号：US6133116A

公开(公告)日：2000-10-17

申请号：US328708

申请日：1999-06-09

Applicant: Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Gyu Lee

Inventor： Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Gyu Lee

IPC: H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/8238

CPC classification number: H01L27/10844 ,  H01L21/762 ,  H01L21/765 ,  H01L27/10805 ,  H01L27/10873

Abstract: Narrow-channel effect free DRAM cell transistor structure for submicron isolation pitch DRAMs having lowed-doped substrate and active width-independent threshold voltage by employing conductive shield in the shallow trench isolation(STI). The resulting cell transistor structure is highly immune to parasitic E-field penetration from the gate and neighbouring storage node junctions via STI and will be very appropriate for Gbit scale DRAM technology. The conductive shield is biased with the negative voltage in order to minimize the sidewall depletion in the substrate.

Abstract translation: 通过在浅沟槽隔离（STI）中采用导电屏蔽，具有低掺杂衬底和有源宽度无关阈值电压的亚微米隔离间距DRAM的窄通道无效无效DRAM单元晶体管结构。 所得到的单元晶体管结构对通过STI的栅极和相邻存储节点结的寄生E场渗透是高度免疫的，并且将非常适合于Gbit规模DRAM技术。 导电屏蔽被负电压偏压，以便最小化衬底中的侧壁耗尽。

公开(公告)号：US5654928A

公开(公告)日：1997-08-05

申请号：US639261

申请日：1996-04-23

Applicant: Kyu-Chan Lee ,  Jai-Hoon Sim

Inventor： Kyu-Chan Lee ,  Jai-Hoon Sim

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A current sense amplifier for use in a semiconductor memory device having a pair of sub-I/O lines and a pair of I/O lines includes a first circuit leg having a first PMOS transistor in series with a second NMOS transistor. A second circuit leg has a third PMOS transistor in series with a fourth NMOS transistor. The gates of the PMOS transistors are each cross coupled to the drain of the other PMOS transistor. The gates of the NMOS transistor are each cross coupled to the source of the PMOS transistor in the other circuit leg. The source of each PMOS transistor comprises a sub-Input/Output line with an Input/Output line located between the transistors in each of the legs.

Abstract translation: 用于具有一对子I / O线和一对I / O线的半导体存储器件的电流检测放大器包括具有与第二NMOS晶体管串联的第一PMOS晶体管的第一电路支路。 第二电路支路具有与第四NMOS晶体管串联的第三PMOS晶体管。 PMOS晶体管的栅极各自交叉耦合到另一个PMOS晶体管的漏极。 NMOS晶体管的栅极分别与另一个电路支路中的PMOS晶体管的源极交叉耦合。 每个PMOS晶体管的源极包括一个子输入/输出线，其中输入/输出线位于每个支路中的晶体管之间。