公开(公告)号：US06440793B1

公开(公告)日：2002-08-27

申请号：US09757514

申请日：2001-01-10

Applicant: Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

Inventor： Ramachandra Divakaruni ,  Heon Lee ,  Jack A. Mandelman ,  Carl J. Radens ,  Jai-Hoon Sim

IPC: H01L218242

CPC classification number: H01L27/10841 ,  H01L21/2255 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

Abstract: An improved process for making a vertical MOSFET structure comprising: A method of forming a semiconductor memory cell array structure comprising: providing a vertical MOSFET DRAM cell structure having a deposited gate conductor layer planarized to a top surface of a trench top oxide on the overlying silicon substrate; forming a recess in the gate conductor layer below the top surface of the silicon substrate; implanting N-type dopant species through the recess at an angle to form doping pockets in the array P-well; depositing an oxide layer into the recess and etching said oxide layer to form spacers on sidewalls of the recess; depositing a gate conductor material into said recess and planarizing said gate conductor to said top surface of the trench top oxide.

公开(公告)号：US5619467A

公开(公告)日：1997-04-08

申请号：US623790

申请日：1996-03-29

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/409

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A current sense amplifier circuit for a semiconductor memory device includes a differential amplifier which senses the signal currents input to first and second input nodes, amplifies the difference between the two signals and outputs the sense-amplified signals to first and second output nodes. A first feedback circuit is connected between the second input node and a current controlling node and has a controlling terminal connected to the first output node. A second feedback circuit is connected between the first input node and the current controlling node and has a controlling terminal connected to the second output node. By feeding back voltages from the counterpart output nodes through the cross-connected feedback circuits, the difference between low level input signals can be efficiently detected and a stable sense-amplified output is obtained.

Abstract translation: 用于半导体存储器件的电流检测放大器电路包括差分放大器，其感测输入到第一和第二输入节点的信号电流，放大两个信号之间的差，并将读出放大的信号输出到第一和第二输出节点。 第一反馈电路连接在第二输入节点和电流控制节点之间，并且具有连接到第一输出节点的控制终端。 第二反馈电路连接在第一输入节点和当前控制节点之间，并且具有连接到第二输出节点的控制终端。 通过交叉连接反馈电路从对方输出节点反馈电压，可以有效地检测低电平输入信号之间的差异，并获得稳定的读出放大输出。

公开(公告)号：US20120236620A1

公开(公告)日：2012-09-20

申请号：US13420505

申请日：2012-03-14

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: G11C5/06 ,  H01L21/762

CPC classification number: H01L27/228 ,  G11C5/063 ,  G11C11/1659 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2436

Abstract: The present invention relates to a nonvolatile memory device and a manufacturing method thereof, the device comprising a plurality of word lines; a plurality of bit lines perpendicular to the word lines; and a plurality of memory cells including a transistor with a source connected to a source line, a gate, and a drain connected to a memory element, with the other end of the memory element connected to the bit lines. Between memory cells adjacent along a bit line, a gate terminal in a groove between the memory cells connects the gates in the memory cells to a word line. Memory cells adjacent along a word line are connected to one bit line contact point, and memory cells sharing a gate terminal are connected to different bit lines. Bit lines are disposed at the upper portion and source lines at the lower end of the memory cell.

Abstract translation: 非易失性存储器件及其制造方法技术领域本发明涉及非易失性存储器件及其制造方法，该器件包括多个字线; 垂直于字线的多个位线; 以及多个存储单元，包括具有连接到源极线的源极，连接到存储元件的栅极和漏极的晶体管，存储元件的另一端连接到位线。 在沿着位线相邻的存储单元之间，存储单元之间的沟槽中的栅极端子将存储单元中的栅极连接到字线。 沿着字线相邻的存储单元连接到一个位线接触点，并且共享栅极端子的存储单元连接到不同的位线。 位线设置在存储单元下端的上部和源极线处。

公开(公告)号：US07977726B2

公开(公告)日：2011-07-12

申请号：US11896418

申请日：2007-08-31

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: H01L27/108

CPC classification number: H01L28/87 ,  H01L27/1085

Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

Abstract translation: 提供了动态随机存取存储器（DRAM）单元及其制造方法。 DRAM单元包括单元晶体管和单元电容器。 电池电容器包括第一，第二和第三电介质层，以及第一，第二和第三电容器电极。 第一电介质层位于第一电容器电极上。 第二电容器电极位于第一电介质层的顶部。 第二电介质层位于第二电容器电极上。 第三电容器电极位于第二电介质层上并与漏极电连接。 第三电介质层位于第三电容器电极和栅极之间，用于将栅极与第三电容器电极隔离。

公开(公告)号：US20120134195A1

公开(公告)日：2012-05-31

申请号：US13298196

申请日：2011-11-16

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: G11C5/06 ,  H01L21/8239

CPC classification number: H01L27/10823 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891

Abstract: The present invention relates to a memory device having 4F2 size cells and a method for fabricating the same. The memory device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other, and plural memory cells having a transistor that fills a groove between two adjoining memory cells in a direction of the bit lines. A side wall between the two adjoining memory cells is simultaneously covered by an insulating film formed between the gate terminal and the two memory cells. The gate terminal is connected electrically to a word line, drain terminals of two adjoining memory cells are connected electrically to a bit line, and the gate and drain terminals are alternately arranged. One of the plural memory cells is buried in the substrate, and is electrically connected with a substrate or a well formed in the substrate.

Abstract translation: 本发明涉及具有4F2尺寸单元的存储器件及其制造方法。 存储器件包括在一个方向上彼此平行布置的多个字线，彼此平行布置的多个位线，以及具有晶体管的多个存储器单元，该晶体管沿位线的方向填充两个相邻的存储单元之间的沟槽。 两个相邻的存储单元之间的侧壁同时由形成在栅极端子和两个存储单元之间的绝缘膜覆盖。 栅极端子与字线电连接，两个相邻存储单元的漏极端子与位线电连接，栅极和漏极端子交替布置。 多个存储单元中的一个被埋在衬底中，并且与形成在衬底中的衬底或阱电连接。

公开(公告)号：US06329249B1

公开(公告)日：2001-12-11

申请号：US09333574

申请日：1999-06-15

Applicant: Won-Suk Yang ,  Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Kyu Lee

Inventor： Won-Suk Yang ,  Ki-Nam Kim ,  Jai-Hoon Sim ,  Jae-Kyu Lee

IPC: H01L218234

CPC classification number: H01L27/10844 ,  H01L21/823462

Abstract: A method for fabricating a semiconductor device with different gate oxide layers. Oxidation is controlled in accordance with the active area dimension so that oxide grows thin at a wider active width (peripheral region) and grows thickly at a narrower active width (cell array region). A gate pattern is formed on a semiconductor substrate having different active areas. Gate spacers are formed and then active dimension dependent oxidation process is performed to grow the oxide layers differently from one another.

Abstract translation: 一种制造具有不同栅氧化层的半导体器件的方法。 根据有源面积尺寸控制氧化，使得氧化物在较宽的有源宽度（周边区域）上生长较薄，并且以较窄的有效宽度（电池阵列区域）厚厚地生长。 在具有不同有源区的半导体衬底上形成栅极图案。 形成栅极隔离物，然后进行活性尺寸依赖氧化工艺以使氧化物层彼此不同地生长。

公开(公告)号：US5946243A

公开(公告)日：1999-08-31

申请号：US85569

申请日：1998-05-27

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: H01L21/8242 ,  G11C8/08 ,  G11C11/407 ,  G11C11/408 ,  H01L27/108 ,  G11C7/00

CPC classification number: G11C8/08 ,  G11C11/4085

Abstract: Driving circuits with active body pull-capability for inhibiting boost delay include main, subordinate and boosted signal lines and a first driver circuit electrically coupled to the main signal line, to drive the main signal line at a first potential (e.g., Vcc). A second driver circuit, electrically coupled to the boosted signal line, is also provided to drive the boosted signal line at a second potential (e.g., Vpp) greater than the first potential. A first field effect transistor is provided as a pull-up transistor which has a gate, drain and source electrically coupled to the main signal line, the boosted signal line and the subordinate signal line, respectively. To reduce body-bias effects which might inhibit the speed and pull-up capability of the pull-up transistor, a second field effect transistor is provided to actively pull-up the body (e.g., active region) of the pull-up transistor. This second field effect has a gate, drain and source electrically coupled to the main signal line (or boosted signal line), the boosted signal line and the body of the pull-up transistor, respectively. The second field effect transistor is designed to provide a pull-up function to the body of the pull-up transistor so that the magnitude of the reverse bias between an inversion layer channel (e.g., N-type) and the body region (e.g., P-type) of the pull-up transistor is reduced when the pull-up transistor is turned on to provide a voltage boost to the subordinate signal line. This reduction in the reverse bias results in a reduction of the body-bias effect and the increase in threshold voltage typically associated with the body-bias effect.

Abstract translation: 具有用于抑制升压延迟的具有主体拉动能力的驱动电路包括主，从属和升压的信号线，以及电耦合到主信号线的第一驱动电路，以以第一电位（例如，Vcc）驱动主信号线。 还提供电耦合到升压信号线的第二驱动器电路，以在大于第一电位的第二电位（例如Vpp）下驱动升压信号线。 第一场效应晶体管被提供为上拉晶体管，其具有电耦合到主信号线，升压信号线和从属信号线的栅极，漏极和源极。 为了减少可能抑制上拉晶体管的速度和上拉能力的体偏置效应，提供第二场效应晶体管以主动上拉上拉晶体管的主体（例如，有源区）。 该第二场效应具有分别与主信号线（或升压信号线），升压信号线和上拉晶体管的主体电耦合的栅极，漏极和源极。 第二场效应晶体管被设计为向上拉晶体管的主体提供上拉功能，使得反向层通道（例如，N型）与体区之间的反向偏置的大小（例如， 当上拉晶体管导通时，上拉晶体管的P型减小，以向下级信号线提供升压。 反向偏置的这种减少导致身体偏置效应的降低和通常与体偏置效应相关联的阈值电压的增加。

公开(公告)号：US20090057741A1

公开(公告)日：2009-03-05

申请号：US11896418

申请日：2007-08-31

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L28/87 ,  H01L27/1085

Abstract: A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

Abstract translation: 提供了动态随机存取存储器（DRAM）单元及其制造方法。 DRAM单元包括单元晶体管和单元电容器。 电池电容器包括第一，第二和第三电介质层，以及第一，第二和第三电容器电极。 第一电介质层位于第一电容器电极上。 第二电容器电极位于第一电介质层的顶部。 第二电介质层位于第二电容器电极上。 第三电容器电极位于第二电介质层上并与漏极电连接。 第三电介质层位于第三电容器电极和栅极之间，用于将栅极与第三电容器电极隔离。

公开(公告)号：US5703475A

公开(公告)日：1997-12-30

申请号：US671145

申请日：1996-06-24

Applicant: Kyu-Chan Lee ,  Jai-Hoon Sim

Inventor： Kyu-Chan Lee ,  Jai-Hoon Sim

IPC: G11C11/413 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  G05F3/16

CPC classification number: G05F3/242

Abstract: A reference voltage generator includes a pull-up stage which pulls a reference voltage signal rapidly up toward 1/2Vcc at power-up. The pull-up stage is controlled by a controller which has a comparator and control voltage generator which are disabled after the pull-up operation is terminated so as to reduce stand-by current consumption. The controller includes a pair of NAND gates cross connected as an RS flip-flop to turn on the pull-up stage at power up. A boost signal allows the flip-flop to enable the comparator and control voltage generator after the power supply has stabilized. When the reference voltage signal reaches 1/2Vcc, the comparator sets the flip flop which turns off the pull-up stage and disables the comparator and control voltage generator.

Abstract translation: 一个参考电压发生器包括一个上拉电平，它在上电时将参考电压信号快速上升至+ E，加1/2 + EE Vcc。 上拉级由控制器控制，控制器具有比较器和控制电压发生器，在上拉操作结束后禁止，以减少待机电流消耗。 控制器包括一对NAND门，它们作为RS触发器交叉连接，以在上电时接通上拉电平。 升压信号允许触发器在电源稳定后使能比较器和控制电压发生器。 当参考电压信号达到+ E，fra 1/2 + EE Vcc时，比较器设置关闭上拉电平的触发器，并禁止比较器和控制电压发生器。

公开(公告)号：US5656946A

公开(公告)日：1997-08-12

申请号：US590301

申请日：1996-01-23

Applicant: Jai-Hoon Sim

Inventor： Jai-Hoon Sim

IPC: G11C11/407 ,  G11C5/14 ,  H03K17/16

CPC classification number: G11C5/143

Abstract: A voltage driving circuit for use in a semiconductor memory device. The voltage driving circuit includes a generator which generates a first voltage for an operating mode of the device, a generator which generates a second voltage for a standby mode, and a pair of switches connected between the voltage generators and an operating circuit, for selectively supplying the first and second voltages thereto. The first and second switches each have a control terminal, both of which are commonly coupled to a mode signal, for allowing external control of the voltage selection. The first and second voltages are preferably set relative to each other so as to reduce the subthreshold leakage current consumed by the semiconductor memory during a standby mode, while maintaining a desired operating speed during an operating mode.

Abstract translation: 一种用于半导体存储器件的电压驱动电路。 电压驱动电路包括产生用于器件工作模式的第一电压的发生器，产生用于待机模式的第二电压的发生器和连接在电压发生器和操作电路之间的一对开关，用于选择性地供电 第一和第二电压。 第一和第二开关各自具有控制端子，两者都通常耦合到模式信号，用于允许电压选择的外部控制。 优选地，第一和第二电压相对于彼此设置，以便在待机模式期间减少由半导体存储器消耗的亚阈值泄漏电流，同时在操作模式期间保持期望的操作速度。