Abstract:
An apparatus for performance improvement of a burst mode digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot.
Abstract:
An apparatus for performance improvement of a burst mode digital wireless receiver comprises a processing circuit for processing a plurality of receiv ed signals and providing a processed signal and a delay circuit for introducing a predeterm ined delay to the processed signal. The delay circuit is coupled to the processing circuit . The predetermined delay is such that the processed signal is delayed to correspo nd with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The pro cessing circuit weights and combines the received signals using a predetermined symb ol pattern within a sync sequence within a time slot.
Abstract:
An apparatus for performance improvement of a burst mode digital wireless receiver comprises a processing circuit for processing a plurality of received signals and providing a processed signal and a delay circuit for introducing a predetermined delay to the processed signal. The delay circuit is coupled to the processing circuit. The predetermined delay is such that the processed signal is delayed to correspond with a later data burst. The processing circuit weights and combines the received signals, where the processing circuit reduces a mean squared error of an output signal. The processing circuit weights and combines the received signals using a predetermined symbol pattern within a sync sequence within a time slot.
Abstract:
A communication system and method, particularly adapted for use in adaptive antenna arrays, are presented. A plurality of signals containing a desired signal, interference, and noise are received through an array of antennas connected to a base receiving station. The signal arriving at each antenna is weighted according to computations which adjust those weights as a function of received interference and noise power in an unequal manner, based on the estimation accuracy of the interference and noise, which in turn depends on factors such as interference to noise power ratios and fading rate.