PERIPHERAL SUPPLIED ADDRESSING IN A SIMPLE DMA
    11.
    发明申请
    PERIPHERAL SUPPLIED ADDRESSING IN A SIMPLE DMA 审中-公开
    外部提供简单的DMA寻址

    公开(公告)号:WO2008014244A2

    公开(公告)日:2008-01-31

    申请号:PCT/US2007074194

    申请日:2007-07-24

    CPC classification number: G06F13/28

    Abstract: A method of performing a direct memory access has the steps of selecting a peripheral device for performing a direct memory access through a direct memory access controller; providing a partial address by the peripheral device to the direct memory access controller; and forming the source or destination address by combining the partial address with selected bits from a source register within the direct memory access controller.

    Abstract translation: 执行直接存储器访问的方法具有选择用于通过直接存储器访问控制器执行直接存储器访问的外围设备的步骤; 通过所述外围设备向所述直接存储器访问控制器提供部分地址; 以及通过将部分地址与来自直接存储器访问控制器内的源寄存器的选定位组合来形成源或目的地地址。

    13.
    发明专利
    未知

    公开(公告)号:DE60037625T2

    公开(公告)日:2008-12-24

    申请号:DE60037625

    申请日:2000-09-21

    Abstract: A radio frequency transponder device in an integrated circuit package requires only one dedicated pin for connection to a parallel resonant tuned circuit for receiving a remote signal. The one dedicated pin has a capacitor which blocks direct current (DC) flow and allows independent DC biasing of a radio frequency amplifier for increased signal amplification gain. Another package pin used for common power or ground connections supplies the second connection to the resonant tuned circuit. Multiple transponder inputs may be implemented in a single integrated circuit package using only one dedicated pin per input plus one common pin which may be used for another purpose, such as a power or a ground connection.

    14.
    发明专利
    未知

    公开(公告)号:DE60033752D1

    公开(公告)日:2007-04-19

    申请号:DE60033752

    申请日:2000-09-22

    Abstract: An electronic system, comprising a digital processor and an EEPROM, has circuit logic and program software or firmware for determining if a programming voltage level is sufficient for reliably programming the EEPROM. A charge pump is enabled and generates a voltage used for programming of the EEPROM. The enabled charge pump thereby loads a battery power supply. In addition, a test load may be connected to the output of the charge pump to simulate the EEPROM load during a programming operation to the EEPROM. The charge pump output voltage is measured to determine if at least a desired voltage value is obtained. Once the charge pump voltage level has been pre-qualified for the desired voltage value, an actual programming operation to the EEPROM may be performed. If the voltage level does not reach the desired value then a programming operation is inhibited and the electronic system may alarm or shut down operation. The charge pump voltage level is a good indication and measure of battery charge condition under actual EEPROM programming load conditions.

    15.
    发明专利
    未知

    公开(公告)号:BR0004417A

    公开(公告)日:2001-10-23

    申请号:BR0004417

    申请日:2000-09-25

    Abstract: A radio frequency transponder device in an integrated circuit package requires only one dedicated pin for connection to a parallel resonant tuned circuit for receiving a remote signal. The one dedicated pin has a capacitor which blocks direct current (DC) flow and allows independent DC biasing of a radio frequency amplifier for increased signal amplification gain. Another package pin used for common power or ground connections supplies the second connection to the resonant tuned circuit. Multiple transponder inputs may be implemented in a single integrated circuit package using only one dedicated pin per input plus one common pin which may be used for another purpose, such as a power or a ground connection.

    17.
    发明专利
    未知

    公开(公告)号:DE69727273D1

    公开(公告)日:2004-02-26

    申请号:DE69727273

    申请日:1997-02-21

    Abstract: According to the present invention, a method is provided for reading data from non-volatile memory in an electronic encoding device such that unauthorized access to the data is prevented. In one embodiment, the method includes the steps of writing a first set of data to the non-volatile memory; generating a voltage detect signal during the writing, the voltage detect signal being representative of a source voltage applied to the non-volatile memory; determining whether the writing was successful by evaluating the voltage detect signal; and reading data from the non-volatile memory responsive to the determination.

    18.
    发明专利
    未知

    公开(公告)号:DE69900626D1

    公开(公告)日:2002-01-31

    申请号:DE69900626

    申请日:1999-03-24

    Abstract: A transmitter system having an adjustable monolithic frequency stabilization and tuning internal capacitor circuit. The transmitter system has a transmitter for generating and transmitting a transmitter oscillator frequency signal. A data generating chip is coupled to the transmitter. The data generating chip is used for adjusting and controlling the transmitter oscillator frequency signal. A variable capacitor circuit is located internal to the data generating chip and is coupled to a ground pin and one of a plurality of function pins on the data generating chip. The variable capacitor circuit is used for adjusting and setting the centerpoint of the transmitter oscillator frequency signal.

    19.
    发明专利
    未知

    公开(公告)号:AT382982T

    公开(公告)日:2008-01-15

    申请号:AT00120633

    申请日:2000-09-21

    Abstract: A radio frequency transponder device in an integrated circuit package requires only one dedicated pin for connection to a parallel resonant tuned circuit for receiving a remote signal. The one dedicated pin has a capacitor which blocks direct current (DC) flow and allows independent DC biasing of a radio frequency amplifier for increased signal amplification gain. Another package pin used for common power or ground connections supplies the second connection to the resonant tuned circuit. Multiple transponder inputs may be implemented in a single integrated circuit package using only one dedicated pin per input plus one common pin which may be used for another purpose, such as a power or a ground connection.

    20.
    发明专利
    未知

    公开(公告)号:DE69715117T2

    公开(公告)日:2003-05-08

    申请号:DE69715117

    申请日:1997-02-21

    Abstract: According to the present invention there is provided an encoder, which in one embodiment, includes a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value such that only one bit of the counter value changes each time the counter value is incremented, a non-volatile memory for storing the counter value, and a transmitter which transmits the output code and the counter value. In another embodiment of the invention there is provided a method for use with an encoder having a processing circuit which generates an output code according to an encoding algorithm, a counter circuit for incrementing a counter value, a non-volatile memory for storing the counter value, and a transmitter which transmits the output code and the counter value. In one embodiment, the method includes the steps of incrementing the counter value such that only one bit is changed each time the counter is incremented. In still a further embodiment the method includes the steps of using a semaphore register and determining whether the semaphore register is set to 0.

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