公开(公告)号：WO1997007512A1

公开(公告)日：1997-02-27

申请号：PCT/US1996012854

申请日：1996-08-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MERRITT, Todd, A. ,  DUESMAN, Kevin

IPC: G11C07/00

CPC classification number: G11C5/145 ,  G11C11/4074 ,  G11C17/16

Abstract: A voltage generator is provided for use in a DRAM to generate an appropriate voltage for programming antifuses. This voltage generator is preferably implemented using a charge pump to generate the high voltage necessary for programming antifuses.

Abstract translation: 提供了一种用于DRAM的电压发生器，以产生用于编程反熔丝的适当电压。 该电压发生器优选地使用电荷泵来实现以产生编程反熔丝所需的高电压。

公开(公告)号：WO1996041345A1

公开(公告)日：1996-12-19

申请号：PCT/US1996010176

申请日：1996-06-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SCHAEFER, Scott

IPC: G11C07/00

CPC classification number: G11C11/4076 ,  G11C7/12 ,  G11C7/22 ,  G11C8/06

Abstract: A synchronous dynamic random access memory (SDRAM) includes a memory array and is responsive to command signals and address bits. A command decoder/controller responds to selected command signals to initiate, at different times, a precharge command, an active command, and a transfer command. The command decoder/controller initiates the active command during the precharge command. Indicating circuitry responds to the precharge command to provide a precharge complete signal indicating the completion of a precharge command operation. A row address latch responds to the active command to receive and hold a value representing a row address of the memory array as indicated by the address bits provided at the time the active command is initiated, and responds to the precharge complete signal to release the row address.

Abstract translation: 同步动态随机存取存储器（SDRAM）包括存储器阵列并响应命令信号和地址位。 命令解码器/控制器响应所选择的命令信号，以在不同的时间启动预充电命令，活动命令和传送命令。 命令解码器/控制器在预充电命令期间启动活动命令。 指示电路响应预充电命令以提供指示预充电命令操作完成的预充电完成信号。 行地址锁存器响应活动命令以接收和保持表示存储器阵列的行地址的值，如由激活命令启动时提供的地址位所指示的，并响应预充电完成信号以释放行 地址。

公开(公告)号：WO1996031882A1

公开(公告)日：1996-10-10

申请号：PCT/US1995016071

申请日：1995-12-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SEYYEDY, Mir, Majid

IPC: G11C07/00

CPC classification number: G11C29/81 ,  G11C7/18 ,  G11C11/4097

Abstract: An integrated memory array circuit, such as a DRAM, has global array bit lines each of which is connected hierarchically above a plurality of electrically isolatable subarray bit lines. Each subarray bit line is connected hierarchically above a pluratity of memory cells. The memory cells are selectively coupled to the subarray bit lines using word lines. Data stored on the memory cells can be left floating, or can be refreshed in temporary storage on both the global array bit lines and the electrically isolatable subarray bit lines which have sufficient capacitance to maintain readily accessible data in temporary storage.

Abstract translation: 诸如DRAM的集成存储器阵列电路具有全局阵列位线，每个阵列位线分层连接在多个电隔离子阵列位线之上。 每个子阵列位线分层连接在多个存储单元上。 使用字线选择性地将存储单元耦合到子阵列位线。 存储在存储器单元上的数据可以被悬空，或者可以在具有足够电容的全局阵列位线和电隔离子阵列位线上的临时存储器中刷新以在临时存储器中维持容易访问的数据。

公开(公告)号：WO1996027032A1

公开(公告)日：1996-09-06

申请号：PCT/US1996001773

申请日：1996-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WESTMORELAND, Donald, L. ,  SANDHU, Gurtej, S.

IPC: C23C16/44

CPC classification number: C23C16/4485

Abstract: The invention is a method directed to the use of a precursor, either a solid precursor or a liquid precursor, suitable for chemical vapor deposition (CVD), including liquid source CVD (LSCVD), of a semiconductor film. Using the method of the invention the precursor is dissolved in a solvent. The choice of solvent is typically an inorganic compound that has a moderate to high vapor pressure at room temperature and that can be liquified by a combination of pressure and cooling. The solution thus formed is then transported at an elevated pressure and/or a reduced temperature to the CVD chamber. In CVD the solution evaporates at a higher temperature and a lower pressure upon entry to the CVD chamber, and the precursor, in its gaseous state, along with a gas reactant, produces a product which is deposited as a thin film on a semiconductor wafer. In LSCVD the liquid enters the chamber, contacts the wafer, evaporates, produces a product which is deposited as a thin film on the wafer surface.

Abstract translation: 本发明涉及一种适用于半导体膜的化学气相沉积（CVD）（包括液体源CVD（LSCVD））的前体，即固体前体或液体前体的方法。 使用本发明的方法，将前体溶解在溶剂中。 溶剂的选择通常是在室温下具有中等至高蒸气压的无机化合物，并且可以通过压力和冷却的组合液化。 然后将如此形成的溶液在升高的压力和/或降低的温度下输送到CVD室。 在CVD中，溶液在进入CVD室时在更高的温度和更低的压力下蒸发，并且处于气态的前体与气体反应物一起产生在半导体晶片上作为薄膜沉积的产物。 在LSCVD中，液体进入腔室，接触晶片，蒸发，产生在晶片表面上作为薄膜沉积的产品。

公开(公告)号：WO1996024839A3

公开(公告)日：1996-08-15

申请号：PCT/US1996001027

申请日：1996-01-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MEIKLE, Scott, G. ,  HUDSON, Guy, F.

IPC: B24B37/04

公开(公告)号：WO1996020480A1

公开(公告)日：1996-07-04

申请号：PCT/US1995016795

申请日：1995-12-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WILLIAMS, Brett, L.

IPC: G11C07/00

CPC classification number: G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/407

Abstract: A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of determining the type of memory present allows the system to adjust internal memory access signals in accordance with the type of memory installed. The system may be shipped with a first type of memory, and then upgraded to a second type of memory by the user to improve overall system performance. A first bank of memory may be of a first type, and a second bank may be of another type. The user may make cost versus performance decisions when upgrading memory types or capacities.

Abstract translation: 系统能够接收快速页面模式，扩展数据输出模式，突发扩展数据输出模式或这些存储设备的组合。 确定存储器类型的方法允许系统根据安装的存储器的类型来调整内部存储器访问信号。 该系统可能随第一类型的存储器一起提供，然后由用户升级到第二类型的存储器以提高整体系统性能。 第一存储器组可以是第一类型，并且第二存储体可以是另一种类型。 升级内存类型或容量时，用户可能会做出成本与性能决定。

公开(公告)号：WO1996020479A1

公开(公告)日：1996-07-04

申请号：PCT/US1995016656

申请日：1995-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ONG, Adrian, E. ,  ZAGAR, Paul, S. ,  WILLIAMS, Brett, L. ,  MANNING, Troy, A.

IPC: G11C07/00

CPC classification number: G11C7/109 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/407

Abstract: An integrated memory circuit is described which has a counter for producing a sequential or interleaved address sequence. The addresses produced are used to access memory elements in a Burst Extended Data Output Dynamic Random Access Memory (Burst EDO or BEDO DRAM). The address is changed in response to a rising edge of a column address signal (CAS*). The memory also includes a buffer circuit which latches the output of the address counter in response to the falling edge of the column address signal. Memory cells are accessed in a burst manner on the falling edge of the column address signal using the address latched in the buffer. The memory includes a generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals. Outputs of the counter are compared with outputs of an input address latch to detect the end of a burst sequence and initialize the device for another burst access.

Abstract translation: 描述了具有用于产生顺序或交错地址序列的计数器的集成存储器电路。 所产生的地址用于访问突发扩展数据输出动态随机存取存储器（Burst EDO或BEDO DRAM）中的存储器元件。 响应于列地址信号（CAS *）的上升沿改变地址。 存储器还包括缓冲电路，其响应于列地址信号的下降沿而锁存地址计数器的输出。 使用缓冲器中锁存的地址，在列地址信号的下降沿以突发方式访问存储单元。 存储器包括用于基于外部列地址信号产生内部控制信号的发生器电路。 发生器电路检测列地址信号的第一有效转换和列地址信号的第一无效转换。 将计数器的输出与输入地址锁存器的输出进行比较，以检测突发序列的结束，并初始化设备以进行另一个突发存取。

公开(公告)号：WO1996020446A1

公开(公告)日：1996-07-04

申请号：PCT/US1995016976

申请日：1995-12-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WILLIAMS, Brett, L.

IPC: G06F12/06

CPC classification number: G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/407

Abstract: A system with a microprocessor has a main memory which is divided into a first burst access memory subsystem tightly coupled to a microprocessor data bus for optimum performance, and a second memory subsystem which is loosely coupled to the microprocessor through a data buffer to provide high memory capacity without heavily loading the microprocessor bus. The second memory subsystem may be burst access or page mode memory. A portion of the second memory subsystem may serve as a video frame buffer.

Abstract translation: 具有微处理器的系统具有主存储器，其被分成紧密耦合到微处理器数据总线以实现最佳性能的第一突发存取存储器子系统，以及通过数据缓冲器松散地耦合到微处理器以提供高存储器的第二存储器子系统 容量而不会大量加载微处理器总线。 第二存储器子系统可以是突发存取或页面模式存储器。 第二存储器子系统的一部分可以用作视频帧缓冲器。

公开(公告)号：WO1996017355A1

公开(公告)日：1996-06-06

申请号：PCT/US1995015558

申请日：1995-11-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ZAGAR, Paul

IPC: G11C11/407

CPC classification number: G11C11/4076 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1072 ,  G11C11/404 ,  G11C11/4045 ,  G11C11/4096

Abstract: An integrated circuit memory device has two banks of NAND structured memory cells and a clock input for synchronously latching control, address and data signals. Time delays of sequentially accessing and restoring memory bits in the NAND structure are masked through the use of the dual bank architecture and synchronous timing. The NAND structured memory cells provide an extremely dense memory array for a high capacity memory device. The input clock signal driving a synchronous word line generator provides a simplified high speed access to the array. A set of random access storage registers temporarily store data from the array and provide high speed page access to an entire page of data from each bank of the memory. The ability to access one bank while simultaneously opening or closing a row in the other bank allows for an unlimited number of high speed sequential data accesses.

Abstract translation: 集成电路存储器件具有两组NAND结构的存储器单元和用于同步地锁存控制，地址和数据信号的时钟输入。 通过使用双存储体架构和同步定时，对NAND结构中的顺序访问和恢复存储器位的时间延迟进行掩蔽。 NAND结构化存储器单元为高容量存储器件提供非常密集的存储器阵列。 驱动同步字线发生器的输入时钟信号提供对阵列的简化的高速访问。 一组随机访问存储寄存器临时存储阵列中的数据，并提供从存储器的每个存储体的整个数据页面的高速页面访问。 在同时打开或关闭另一个行中的一行时访问一个存储体的能力允许无限数量的高速顺序数据访问。

公开(公告)号：WO1996012995A1

公开(公告)日：1996-05-02

申请号：PCT/US1995013252

申请日：1995-10-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  CASPER, Stephen, L.

IPC: G05F01/10

CPC classification number: G05F1/465

Abstract: A power-efficient power regulation circuit (14) for use in semiconductor circuit (10) powered by a power signal includes an N-channel transistor (74) which provides a regulated power signal having a stabilized voltage level for use by the semiconductor circuit. A bias pull-up circuit (70) is coupled to the gate of the N-channel transistor (74) and arranged for biasing the N-channel transistor (74) so that it normally conducts current, and a resistive circuit (76), including a resistive element (100, 104) arranged in series with a resistor-arranged P-channel transistor (102), is coupled to the source of the N-channel transistor (74) and, in response to the regulated power signal (VCCR), provides a feedback control signal (96). A voltage control circuit (72), coupled to the bias pull-up circuit (70) and the resistive circuit (76), is activated to control the N-channel transistor (74) in response to the feedback control signal (96). The voltage control circuit may include an enabling transistor (75) which is activated to enable the voltage control circuit.

Abstract translation: 用于由功率信号供电的半导体电路（10）的功率有效的功率调节电路（14）包括N沟道晶体管（74），其提供具有用于半导体电路的稳定电压电平的稳压电源信号。 偏置上拉电路（70）耦合到N沟道晶体管（74）的栅极，并被布置成用于偏置N沟道晶体管（74），使得其通常导通电流，并且电阻电路（76） 包括与电阻器布置的P沟道晶体管（102）串联布置的电阻元件（100,104）耦合到N沟道晶体管（74）的源极，并且响应于稳定的功率信号（VCCR ），提供反馈控制信号（96）。 耦合到偏置上拉电路（70）和电阻电路（76）的电压控制电路（72）被激活，以响应于反馈控制信号（96）来控制N沟道晶体管（74）。 电压控制电路可以包括使能晶体管（75），其被激活以使能电压控制电路。