11.
    发明专利
    未知

    公开(公告)号:BR9105788A

    公开(公告)日:1992-08-04

    申请号:BR9105788

    申请日:1991-05-17

    Applicant: MOTOROLA INC

    Inventor: JASPER STEVEN C

    Abstract: A quad 16 QAM transmission and reception methodology wherein a time domain pilot reference is advantageously associated therewith. There may be one or more such pilot references (402) for each packet of multiple 16 QAM pulses. Depending upon the embodiment, each 16 QAM pulse can include a time domain pilot reference, or an estimated pilot reference for that pulse can be determined either by reference to pilot references in other pulses sharing the same packet, or by reference to pilot references for other previously received 16 QAM pulses corresponding to that same pulse.

    COMMUNICATION SIGNAL HAVING A TIME DOMAIN PILOT COMPONENT

    公开(公告)号:AU7951491A

    公开(公告)日:1992-01-07

    申请号:AU7951491

    申请日:1991-05-17

    Applicant: MOTOROLA INC

    Inventor: JASPER STEVEN C

    Abstract: A quad 16 QAM transmission and reception methodology wherein a time domain pilot reference is advantageously associated therewith. There may be one or more such pilot references (402) for each packet of multiple 16 QAM pulses. Depending upon the embodiment, each 16 QAM pulse can include a time domain pilot reference, or an estimated pilot reference for that pulse can be determined either by reference to pilot references in other pulses sharing the same packet, or by reference to pilot references for other previously received 16 QAM pulses corresponding to that same pulse.

    PHASE CORRECTED CLOCK SIGNAL RECOVERY CIRCUIT

    公开(公告)号:CA1185332A

    公开(公告)日:1985-04-09

    申请号:CA381016

    申请日:1981-07-02

    Applicant: MOTOROLA INC

    Abstract: A phase corrected clock signal recovery circuit for multilevel digital signals includes a transition marker generator for generating a narrow width pulse each time a received multilevel digital signal crosses one of the threshold levels between the adjacent logic levels of multilevel signal. Picket fence-like pulse trains are thus formed, the pulses (transition markers) of which correspond to the threshold crossings of the received digital signal, The pulse trains are interspersed with spaces or eye intervals which correspond to the absence of any threshold crossings. Each eye interval additionally corresponds to the time during which each respective bit of digital signal information is transmitted. The rate of occurrence of the pulse trains is substantially equal to the clock frequency of the received digital signal. A phase error correction circuit is operatively coupled to the output of the transition marker generator and to an electronically tuned bandpass filter capable of adjusting the phase of the pulse trains. More specifically, the phase error detection circuit includes an up/down counter and adjusts the phase of the clock signal recovered from the pulse trains such that the number of transition markers generated during the high portion of the clock signal equals the number of transition markers generated during the low portion of the clock signal. Thus, selected transitory edges of the pulses of the recovered clock signal are centered at the middles of the respective eye intervals, that is, at the points in time when each respective bit of multilevel digital signal information occurs. This phase corrected recovered clock signal is conveniently applied to appropriate sampling circuitry to enable sampling of the multilevel digital signal at optimum times, that is, at the center of the eye intervals.

    APPARATUS AND METHOD FOR ATTENUATING INTERFERING SIGNALS

    公开(公告)号:CA1165841A

    公开(公告)日:1984-04-17

    申请号:CA391505

    申请日:1981-12-04

    Applicant: MOTOROLA INC

    Abstract: A method and apparatus for attenuating an interfering signal corrupting a desired Loran C signal is provided. An interfering signal sample is determined which occurs at the peak of the autocorrelation function of the interfering signal such that the period of the interferer is known. The sample occurring at the peak of the autocorrelation function is added to or subtracted from the desired Loran C signal sample taken at a predetermined reference point during the pulses thereof such that the interfering signal is cancelled or substantially attenuated.

    METHOD AND APPARATUS FOR USING A PSEUDO-RANDOM SIGNAL IN A COMMUNICATION SYSTEM
    15.
    发明公开
    METHOD AND APPARATUS FOR USING A PSEUDO-RANDOM SIGNAL IN A COMMUNICATION SYSTEM 审中-公开
    VERFAHREN UNDGERÄTZUR VERWENDUNG EINES PSEUDO-ZUFÄLLIGEN信号在EINEM KOMMUNIKATIONSSYSTEM

    公开(公告)号:EP1105980A4

    公开(公告)日:2004-03-03

    申请号:EP99939708

    申请日:1999-08-06

    Applicant: MOTOROLA INC

    CPC classification number: G01S5/0221 G01S5/14 G01S11/02 G01S2205/007

    Abstract: The figure shows a base site (104) generating a pseudo-random signal based on at least one system parameter known to both the base site (104) and a communication unit (112). The base site transmitter (106) then transmits the pseudo-random signal to the communication unit via an idle communication resource (102). Upon receiving the pseudo-random signal by the receiver (114) of the communication unit (112) determines at least one characteristic of the idle communication resource (102) using the pseudo-random signal.

    Abstract translation: 基站(104)基于基站和通信单元(112)已知的至少一个系统参数产生伪随机信号。 基站(104)然后经由空闲通信资源(102)将伪随机信号发送到通信单元。 在接收到伪随机信号时,通信单元(112)使用伪随机信号确定空闲通信资源(102)的至少一个特性。

    DIGITAL ZERO-IF SELECTIVITY SECTION.
    16.
    发明公开
    DIGITAL ZERO-IF SELECTIVITY SECTION. 失效
    DIGITALE ZERO-MF SELEKTIVE STUFE。

    公开(公告)号:EP0216803A4

    公开(公告)日:1988-11-02

    申请号:EP86901242

    申请日:1986-01-30

    Applicant: MOTOROLA INC

    CPC classification number: H03D7/166 H03B27/00 H03B28/00 H03C3/40 H03D1/2245

    Abstract: A digital Zero-IF Selectivity Section (DZISS) (20, 20'). The DZISS of the present invention teaches a topology that facilitates realization in both transmitter (20') and receivers (20). In the preferred low-speed embodiment, the digital filters (32, 32', 33, 33') are comprised of cascaded filter sections (64a-64d) employing decimation (66) to reduce the data rate. In the preferred high-speed embodiment, the digital filters (32, 32', 33, 33') are more sophisticated as at least the first filter section (64') is decomposed to enable high-speed operation. Decimation (66) is also employed on the high-speed embodiment to allow subsequent circuitry to operate at a lower data rate thus consuming less power. In an alternate embodiment, applicable to the low-speed and high-speed preferred embodiments, sections of the digital low pass filters (100A, 100B) are time multiplexed (104) effectuating a cost and space savings.

    Abstract translation: 数字零中频选择性部分(DZISS)(20,20')。 本发明的DZISS教导了便于在发射机(20')和接收机(20)中实现的拓扑结构。 在优选的低速实施例中,数字滤波器(32,32',33,33')由采用抽取(66)的级联滤波器部分(64a-64d)组成以降低数据速率。 在优选的高速实施例中,由于至少第一滤波器部分(64')被分解以实现高速操作,因此数字滤波器(32,32',33,33')更复杂。 抽取(66)也用于高速实施例,以允许后续电路以较低的数据速率工作,从而消耗较少的功率。 在可应用于低速和高速优选实施例的替代实施例中,数字低通滤波器(100A,100B)的部分被时分多路复用(104),从而实现成本和空间节省。

    CHANNEL ESTIMATION USING LINEARLY-CONSTRAINED FILTER COEFFICIENTS
    18.
    发明申请
    CHANNEL ESTIMATION USING LINEARLY-CONSTRAINED FILTER COEFFICIENTS 审中-公开
    使用线性约束滤波器系数的信道估计

    公开(公告)号:WO2006107910A2

    公开(公告)日:2006-10-12

    申请号:PCT/US2006012407

    申请日:2006-03-31

    CPC classification number: H04L25/0224 H04L27/2647

    Abstract: A system that includes a receiver (100) that is configured for: selecting (210) a set of demodulator output samples and a corresponding set of reference symbols each having a magnitude; generating (220) a set of raw channel estimates based on the set of demodulator output samples and the corresponding set of reference symbols; determining (230) a set of linearly-constrained filter coefficient parameters; and combining (240) the set of raw channel estimates with the set of linearly-constrained filter coefficient parameters to generate a channel estimate.

    Abstract translation: 一种包括接收机(100)的系统,其被配置为:选择(210)一组解调器输出采样和各自具有幅度的对应的参考符号集合; 基于所述解调器输出样本集合和相应的参考符号集合来生成(220)一组原始信道估计; 确定(230)一组线性约束滤波器系数参数; 以及将所述原始信道估计集合与所述线性约束滤波器系数参数的集合(240)以生成信道估计。

    Maximal ratio diversity combining technique

    公开(公告)号:HK1000528A1

    公开(公告)日:1998-04-03

    申请号:HK97102132

    申请日:1997-11-07

    Applicant: MOTOROLA INC

    Abstract: A method for implementing diversity reception to counteract effects of channel fading on a transmitted information signal. In diversity receive paths, estimates of complex channel gain are computed based upon pilot symbols inserted from time to time in the transmitted information symbol stream. Phase corrected and weighted samples from the diversity paths are summed prior to the decision process. The squared magnitudes of the diversity path channel gains are summed to provide the proper threshold adjustment.

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