公开(公告)号：AU5454786A

公开(公告)日：1986-10-23

申请号：AU5454786

申请日：1986-01-30

Applicant: MOTOROLA INC

Inventor： JASPER STEVEN C ,  LONGLEY LESTER A ,  LAMBERT KATHERINE H

IPC: H03D1/00 ,  H03B27/00 ,  H03B28/00 ,  H03C3/40 ,  H03D1/22 ,  H03D7/16 ,  H03H17/02 ,  H04B1/04 ,  H04B1/30

Abstract: A digital Zero-IF Selectivity Section (DZISS) (20, 20'). The DZISS of the present invention teaches a topology that facilitates realization in both transmitter (20') and receivers (20). In the preferred low-speed embodiment, the digital filters (32, 32', 33, 33') are comprised of cascaded filter sections (64a-64d) employing decimation (66) to reduce the data rate. In the preferred high-speed embodiment, the digital filters (32, 32', 33, 33') are more sophisticated as at least the first filter section (64') is decomposed to enable high-speed operation. Decimation (66) is also employed on the high-speed embodiment to allow subsequent circuitry to operate at a lower data rate thus consuming less power. In an alternate embodiment, applicable to the low-speed and high-speed preferred embodiments, sections of the digital low pass filters (100A, 100B) are time multiplexed (104) effectuating a cost and space savings.

公开(公告)号：CA1318358C

公开(公告)日：1993-05-25

申请号：CA616314

申请日：1992-02-19

Applicant: MOTOROLA INC

Inventor： JANC ROBERT V ,  JASPER STEVEN C ,  LONGLEY LESTER A ,  LAMBERT KATHERINE H ,  TURNEY WILLIAM J ,  LILLIE ROSS J

IPC: H03D1/24 ,  H04B1/10 ,  H04L7/00 ,  H04L23/02

Abstract: DIGITAL RADIO FREQUENCY RECEIVER A digital radio receiver is described. The digital receiver (100) of the present invention contemplates a digital radio receiver which operates on a received analog signal which has been converter to a digital form after preselection at the output of the antenna. The digital receiver (100) of the present invention comprises a preselector (106), a high-speed analog-to-digital (A/D) converter (108), a digitally implemented intermediate-frequency (IF) selectivity section (110) having an output signal at substantially baseband frequencies, and digital signal processor (DSP)circuit (120) performing demodulation and audio filtering. The radio architecture of the present invention is programmably adaptable to virtually every known modulation scheme and is particularly suitable for implementation on integrated circuits.

公开(公告)号：CA1304786C

公开(公告)日：1992-07-07

申请号：CA517169

申请日：1986-08-29

Applicant: MOTOROLA INC

Inventor： JANC ROBERT V ,  JASPER STEVEN C ,  LONGLEY LESTER A ,  LAMBERT KATHERINE H ,  TURNEY WILLIAM J ,  LILLIE ROSS J

IPC: H03H17/02 ,  H03D1/22 ,  H03D3/00 ,  H04B1/26 ,  H04B14/04 ,  H03D1/24 ,  H04L7/00 ,  H04L23/02 ,  H04B1/10

Abstract: DIGITAL RADIO FREQUENCY RECEIVER A digital radio receiver is described. The digital receiver (100) of the present invention contemplates a digital radio receiver which operates on a received analog signal which has been converted to a digital form after preselection at the output of the antenna. The digital receiver (100) of the present invention comprises a preselector (106), a high-speed analog-to-digital (A/D) converter (108), a digitally implemented intermediate-frequency (IF) selectivity section (110) having an output signal at substantially baseband frequencies, and digital signal processor (DSP)circuit (120) performing demodulation and audio filtering. The radio architecture of the present invention is programmably adaptable to virtually every known modulation scheme and is particularly suitable for implementation on integrated circuits.

公开(公告)号：AT87777T

公开(公告)日：1993-04-15

申请号：AT86901242

申请日：1986-01-30

Applicant: MOTOROLA INC

Inventor： JASPER STEVEN C ,  LONGLEY LESTER A ,  LAMBERT KATHERINE H

IPC: H03D1/00 ,  H03B27/00 ,  H03B28/00 ,  H03C3/40 ,  H03D1/22 ,  H03D7/16 ,  H03H17/02 ,  H04B1/04 ,  H04B1/30

Abstract: A digital Zero-IF Selectivity Section (DZISS) (20, 20'). The DZISS of the present invention teaches a topology that facilitates realization in both transmitter (20') and receivers (20). In the preferred low-speed embodiment, the digital filters (32, 32', 33, 33') are comprised of cascaded filter sections (64a-64d) employing decimation (66) to reduce the data rate. In the preferred high-speed embodiment, the digital filters (32, 32', 33, 33') are more sophisticated as at least the first filter section (64') is decomposed to enable high-speed operation. Decimation (66) is also employed on the high-speed embodiment to allow subsequent circuitry to operate at a lower data rate thus consuming less power. In an alternate embodiment, applicable to the low-speed and high-speed preferred embodiments, sections of the digital low pass filters (100A, 100B) are time multiplexed (104) effectuating a cost and space savings.

公开(公告)号：CA1281080C

公开(公告)日：1991-03-05

申请号：CA500739

申请日：1986-01-30

Applicant: MOTOROLA INC

Inventor： JASPER STEVEN C ,  LONGLEY LESTER A ,  LAMBERT KATHERINE H

IPC: H03D1/00 ,  H03B27/00 ,  H03B28/00 ,  H03C3/40 ,  H03D1/22 ,  H03D7/16 ,  H03H17/02 ,  H04B1/04 ,  H04B1/30

Abstract: DIGITAL ZERO-IF SELECTIVITY SECTION A Digital Zero-IF Selectivity Section (DZISS) is disclosed. The DZISS of the present invention teaches a topology that facilitates realization in both transmitters and receivers. In the preferred low-speed embodiment, the digital filter are comprised of cascaded filter sections employing decimation co reduce the data rate. In the preferred high-speed embodiment, the digital filters are more sophisticated as at least the first filter section is decomposed to enable high-speed operation. Decimation is also employed on the high-speed embodiment to allow subsequent circuitry to operate at a lower data rate thus consuming less power. In an alternate embodiment, applicable to the low-speed and high-speed preferred embodiments, sections of the digital lowpass filters are time multiplexed effectuating a cost and space savings.

公开(公告)号：AU573966B2

公开(公告)日：1988-06-23

申请号：AU5454786

申请日：1986-01-30

Applicant: MOTOROLA INC

Inventor： JASPER STEVEN C ,  LONGLEY LESTER A ,  LAMBERT KATHERINE H

IPC: H03D1/00 ,  H03B27/00 ,  H03B28/00 ,  H03C3/40 ,  H03D1/22 ,  H03D7/16 ,  H03H17/02 ,  H04B1/04 ,  H04B1/30

Abstract: A digital Zero-IF Selectivity Section (DZISS) (20, 20'). The DZISS of the present invention teaches a topology that facilitates realization in both transmitter (20') and receivers (20). In the preferred low-speed embodiment, the digital filters (32, 32', 33, 33') are comprised of cascaded filter sections (64a-64d) employing decimation (66) to reduce the data rate. In the preferred high-speed embodiment, the digital filters (32, 32', 33, 33') are more sophisticated as at least the first filter section (64') is decomposed to enable high-speed operation. Decimation (66) is also employed on the high-speed embodiment to allow subsequent circuitry to operate at a lower data rate thus consuming less power. In an alternate embodiment, applicable to the low-speed and high-speed preferred embodiments, sections of the digital low pass filters (100A, 100B) are time multiplexed (104) effectuating a cost and space savings.

公开(公告)号：EP0216803A4

公开(公告)日：1988-11-02

申请号：EP86901242

申请日：1986-01-30

Applicant: MOTOROLA INC

Inventor： JASPER STEVEN C ,  LONGLEY LESTER A ,  LAMBERT KATHERINE H

IPC: H03D1/00 ,  H03B27/00 ,  H03B28/00 ,  H03C3/40 ,  H03D1/22 ,  H03D7/16 ,  H03H17/02 ,  H04B1/04 ,  H04B1/30

CPC classification number: H03D7/166 ,  H03B27/00 ,  H03B28/00 ,  H03C3/40 ,  H03D1/2245

Abstract: A digital Zero-IF Selectivity Section (DZISS) (20, 20'). The DZISS of the present invention teaches a topology that facilitates realization in both transmitter (20') and receivers (20). In the preferred low-speed embodiment, the digital filters (32, 32', 33, 33') are comprised of cascaded filter sections (64a-64d) employing decimation (66) to reduce the data rate. In the preferred high-speed embodiment, the digital filters (32, 32', 33, 33') are more sophisticated as at least the first filter section (64') is decomposed to enable high-speed operation. Decimation (66) is also employed on the high-speed embodiment to allow subsequent circuitry to operate at a lower data rate thus consuming less power. In an alternate embodiment, applicable to the low-speed and high-speed preferred embodiments, sections of the digital low pass filters (100A, 100B) are time multiplexed (104) effectuating a cost and space savings.

Abstract translation: 数字零中频选择性部分（DZISS）（20,20'）。 本发明的DZISS教导了便于在发射机（20'）和接收机（20）中实现的拓扑结构。 在优选的低速实施例中，数字滤波器（32,32'，33,33'）由采用抽取（66）的级联滤波器部分（64a-64d）组成以降低数据速率。 在优选的高速实施例中，由于至少第一滤波器部分（64'）被分解以实现高速操作，因此数字滤波器（32,32'，33,33'）更复杂。 抽取（66）也用于高速实施例，以允许后续电路以较低的数据速率工作，从而消耗较少的功率。 在可应用于低速和高速优选实施例的替代实施例中，数字低通滤波器（100A，100B）的部分被时分多路复用（104），从而实现成本和空间节省。