公开(公告)号：DE69814268T2

公开(公告)日：2004-01-22

申请号：DE69814268

申请日：1998-08-24

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  ARENDS JOHN ,  SCOTT JEFFREY W

IPC: G06F9/40 ,  G06F9/30 ,  G06F9/38

Abstract: A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

公开(公告)号：DE69810064D1

公开(公告)日：2003-01-23

申请号：DE69810064

申请日：1998-10-26

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52

Abstract: A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.

公开(公告)号：AU8888101A

公开(公告)日：2002-04-02

申请号：AU8888101

申请日：2001-09-07

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W ,  MURDOCK BRETT W

IPC: G06F13/28 ,  G06F13/16

Abstract: Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bus for providing a current address and a previous address to memory, a data bus, an execution unit, and a decode control unit. The processing system further includes a fetch unit, coupled to the execution unit, the decode control unit, the address bus, and the data bus, for generating a first sequence signal that when negated indicates that the current address may not be sequential to the previous address, a second sequence signal that when negated indicates that the current address is not sequential to the previous address, and a third sequence signal that when negated indicates that the current address, if it is an instruction address, is not sequential to the previous address that was an instruction address.

公开(公告)号：SG71861A1

公开(公告)日：2000-04-18

申请号：SG1998004357

申请日：1998-10-30

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F

Abstract: A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.

公开(公告)号：WO0225453A3

公开(公告)日：2003-09-25

申请号：PCT/US0128057

申请日：2001-09-07

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W ,  MURDOCK BRETT W

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28

Abstract: Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory having an address bus (114) for providing a current address and a previous address to memory, a data bus (120), an execution unit (202), and a decode control unit (208). The processing system further includes a fetch unit (218), coupled to the execution unit, the decode control unit, the address bus, and the data bus, for generating a first sequence signal (124) that when negated indicates that the current address may not be sequential to the previous address, a second sequence signal (122) that when negated indicates that the current address is not sequential to the previous address, and a third sequence signal (112) that when negated indicates that the current address, if it is an instruction address, is not sequential to the previous address that was an instruction address.

Abstract translation: 本发明的实施例涉及具有顺序地址指示符信号的处理器，也称为序列信号，用于指示何时访问的地址是顺序的。 一个实施例涉及一种用于访问具有用于向存储器提供当前地址和先前地址的地址总线（114）的存储器的处理系统，数据总线（120），执行单元（202）和解码控制单元（208） ）。 所述处理系统还包括一个提取单元（218），耦合到执行单元，解码控制单元，地址总线和数据总线，用于产生第一序列信号（124），当被否定时指示当前地址可以 不等于先前地址的顺序信号，当被否定时指示当前地址不是与先前地址相连的第二序列信号（122），当被否定时表示当前地址的第三序列信号（112） 是一个指令地址，不是前一个作为指令地址的地址的顺序。