公开(公告)号：JP2000029700A

公开(公告)日：2000-01-28

申请号：JP17069799

申请日：1999-06-17

Applicant: MOTOROLA INC

Inventor： LEE WAN LEE ,  MOYER WILLIAM C ,  SCOTT JEFFREY W ,  ARENDS JOHN H

IPC: G06F9/38 ,  G06F9/32

Abstract: PROBLEM TO BE SOLVED: To minimize a clock cycle number by composing the system of a stage where a program loop is defined and a stage where a loop value is determined according to a backward branch instruction. SOLUTION: A data processor 10 is equipped with a CPU 12, a memory 14, a bus interface module 16, and other modules 18 coupled with one another in two directions through a bus 20. The memory 14 is coupled optionally to the outside of the data processor 10 through one or more integrated circuit circuit terminal 24. The CPU12 is coupled optionally to the outside of the data processor 10 through one or more integrated circuit circuit terminal 22. The data processor 10 executes instructions collected in order from the memory 14 until it encounters a variation instruction for a flow such as a branch instruction. In this case, the backward branch instruction executes branching to a target address in the memory 14, defines a program loop, and sets a loop value according to the backward branch instruction.

公开(公告)号：JP2001022593A

公开(公告)日：2001-01-26

申请号：JP2000172537

申请日：2000-06-08

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W ,  MICHAEL D FITZSIMONS

IPC: G06F9/305 ,  G06F9/38 ,  G06F9/48 ,  G06F13/24 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To reduce latency while maintaining a processor throughput at a minimum by comparing a threshold with a count number which is left before a multi-cycle instruction is completed. SOLUTION: A data processing system includes interruptible instructions and uninterruptible instructions. Namely, interruptive recognition is allowed during an instruction on condition that process environment and/or the instruction to be executed is proper. Once the instruction is interrupted during its execution, a partial result of the instruction is discarded and an interruption which is being held is processed. The threshold is used to prevent data from being lost from an instruction which is substantially completed. During the execution of the multi-cycle instruction, the threshold is compared with the count value which is left before the multi-cycle instruction is completed and shows the number of cycles. Thus, the threshold is used to prevent the data from being lost from the instruction which is substantially completed without increasing the maximum interruption latency time of a data processing system.

公开(公告)号：JPH11219302A

公开(公告)日：1999-08-10

申请号：JP31026898

申请日：1998-10-30

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52

Abstract: PROBLEM TO BE SOLVED: To provide a method and a device for affecting subsequent processings in a data processor. SOLUTION: In one embodiment an interruption-recognition delay instruction(IDLY4) is executed, that is recognition of an interruption is delayed for a controlled period, namely, a prescribed time period or a duration of a prescribed number of instructions, or it is delayed with a prescribed condition. Thus, a read/modification/write instruction sequence can be executed without using an exclusive instruction for defining a change processing. The IDLY4 instruction can change a mode wherein subsequent instructions affect a condition bit 38. Consequently, it is judged whether an exceptional processing is generated or not in an interruption non-recognition period after the IDLY4 instruction is executed by using the condition bit 38.

公开(公告)号：JPH11154144A

公开(公告)日：1999-06-08

申请号：JP25936498

申请日：1998-08-28

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  ARENDS JOHN ,  SCOTT JEFFREY W

IPC: G06F9/40 ,  G06F9/30 ,  G06F9/38 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a data processing system equipped with an improved interface between a processor and a coprocessor. SOLUTION: The interface of processor 12/coprocessor 14 for supporting plural coprocessors 14 and 16 uses the function call, return, instruction execution, variable load and store interface instruction of a software style enabling compiler generation. Data are internally moved through register snooping and broadcasting between the processor 12 and the coprocessor 14 by a bidirectional shared bus 28 or clearly moved through the function call, return, variable load and store interface instruction. The load and store interface instructions enables the selective previous increment of a memory address. The bidirectional bus 28 can be driven in both directions in the case of each clock cycle.

公开(公告)号：DE69919081T2

公开(公告)日：2005-01-27

申请号：DE69919081

申请日：1999-06-04

Applicant: MOTOROLA INC

Inventor： LEE LEA HWANG ,  MOYER WILLIAM C ,  SCOTT JEFFREY W ,  ARENDS JOHN H

IPC: G06F9/38 ,  G06F9/32

Abstract: A pipelined data processing system (10) includes an address generation unit (30). The address generation unit (30) includes a target address register (58), a short backward branch (SBB) address register (60), and a count register (74) that makes the execution of small loops more efficient and allows branch folding without fetching the branch instruction.

公开(公告)号：DE69810064T2

公开(公告)日：2003-04-17

申请号：DE69810064

申请日：1998-10-26

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52

Abstract: A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.

公开(公告)号：DE69814268D1

公开(公告)日：2003-06-12

申请号：DE69814268

申请日：1998-08-24

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  ARENDS JOHN ,  SCOTT JEFFREY W

IPC: G06F9/40 ,  G06F9/30 ,  G06F9/38

Abstract: A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

公开(公告)号：AU6302601A

公开(公告)日：2001-12-24

申请号：AU6302601

申请日：2001-05-10

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W

IPC: G06F9/32 ,  G06F9/38

Abstract: A data system capable of selecting whether to utilize address prediction based on the state of an address prediction enable signal. When employing address prediction, the outcome of branch instructions are presumed prior to the resolution of the instruction. When not using address prediction, the system waits until a branch instruction is resolved before fetching the next address to be executed. At least one embodiment of a method and data system disclosed herein makes use of the different setup timing available when employing prediction and non-prediction modes of operation.

公开(公告)号：HK1020218A1

公开(公告)日：2000-03-31

申请号：HK99105223

申请日：1999-11-12

Applicant: MOTOROLA INC

Inventor： MOYER WILLIAM C ,  SCOTT JEFFREY W

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06F

Abstract: A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.

公开(公告)号：DE69919081D1

公开(公告)日：2004-09-09

申请号：DE69919081

申请日：1999-06-04

Applicant: MOTOROLA INC

Inventor： LEE LEA HWANG ,  MOYER WILLIAM C ,  SCOTT JEFFREY W ,  ARENDS JOHN H

IPC: G06F9/38 ,  G06F9/32

Abstract: A pipelined data processing system (10) includes an address generation unit (30). The address generation unit (30) includes a target address register (58), a short backward branch (SBB) address register (60), and a count register (74) that makes the execution of small loops more efficient and allows branch folding without fetching the branch instruction.