公开(公告)号：WO1996001433A1

公开(公告)日：1996-01-18

申请号：PCT/US1995007561

申请日：1995-06-13

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  BOCKELMAN, David, E. ,  EISENSTADT, William, R.

IPC: G01R23/20

CPC classification number: G01R31/3167 ,  G01R1/06772 ,  G01R27/28

Abstract: A method and apparatus is provided for characterizing a differential circuit. A measurement system (200) is used to introduce input signals to the differential circuit and to measure corresponding output signals. Particularly, an input differential wave is introduced into the differential circuit (1010) while correspondingly measuring a differential output wave (1020) and a first common mode output wave (1030). Similarly, an input common mode wave is introduced (1040) while measuring a second differential output wave (1050) and a second common mode output wave (1060).

Abstract translation: 提供了用于表征差分电路的方法和装置。 测量系统（200）用于将输入信号引入差分电路并测量相应的输出信号。 特别地，输入差分波被引入差分电路（1010），同时相应地测量差分输出波（1020）和第一共模输出波（1030）。 类似地，在测量第二差分输出波（1050）和第二共模输出波（1060）的同时引入输入共模波（1040）。

公开(公告)号：WO1995006946A1

公开(公告)日：1995-03-09

申请号：PCT/US1994010004

申请日：1994-08-31

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  BOCKELMAN, David, E. ,  WEISMAN, Douglas, H.

IPC: H01B11/02

CPC classification number: H05K9/0039 ,  H01L23/49838 ,  H01L23/5386 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H04B3/32 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/097 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A twisted-pair conductor line structure is formed on a substrate (22) having insulated conductive layers (10, 11). The conductive layers are used to form first, second, third, and fourth conductive planar segments (16). A first conductive link (17) joins the first and second planar conductive segments to provide a first signal path. Similarly, a second conductive link (17) joins the third and fourth planar conductive segments to provide a second signal path. The first and second conductive links are operatively arranged to form a twist (17) in the first and second signal paths, such that the resulting magnetic fields (57, 59) around the twisted conductive segments will be opposite to each other for cancelling each other out, in order to reduce the magnetic field radiation to the surrounding environment.

Abstract translation: 在具有绝缘导电层（10,11）的基板（22）上形成双绞导体线结构。 导电层用于形成第一，第二，第三和第四导电平面段（16）。 第一导电连接（17）连接第一和第二平面导电段以提供第一信号路径。 类似地，第二导电连接（17）连接第三和第四平面导电段以提供第二信号路径。 第一和第二导电连接件被可操作地布置成在第一和第二信号路径中形成扭转（17），使得围绕扭转的导电段的所得到的磁场（57,59）将彼此相对以抵消彼此 出来，以减少对周围环境的磁场辐射。

公开(公告)号：EP1444783B1

公开(公告)日：2006-12-27

申请号：EP02773869.9

申请日：2002-10-23

Applicant: MOTOROLA, INC.

Inventor： JUAN, Jui-Kuo ,  STENGEL, Robert, E. ,  MARTIN, Frederick, L. ,  BOCKELMAN, David, E.

IPC: H03L7/07 ,  H03L7/081 ,  H03L7/16 ,  H03H11/26

CPC classification number: H03L7/16 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/14 ,  H03L2207/08

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.

公开(公告)号：EP1360791A1

公开(公告)日：2003-11-12

申请号：EP02709427.5

申请日：2002-02-05

Applicant: MOTOROLA, INC.

Inventor： BOCKELMAN, David, E.

IPC: H04L7/00 ,  H03B21/00 ,  H03H11/26 ,  H03L7/00

CPC classification number: G06F1/022 ,  G06F1/10 ,  H03K5/133 ,  H03L7/0812 ,  H03L7/16

Abstract: A digital frequency synthesizer includes a clock which produces a clock signal oscillating at a fixed frequency and a delay line which receives the clock signal and which produces therefrom a plurality of phase shifted clock signals oscillating at the fixed frequency. Each phase shifted clock signal is shifted in phase with respect to the clock signal and with respect to the other phase shifted clock signals. A look-up table receives an address value related to an ideal phase shifted clock signal oscillating at the fixed frequency and outputs a tap address related to the address value. A selection circuit receives the plurality of phase shifted clock signals and the tap address and outputs one of the phase shifted clock signals in response thereto. A sampling circuit samples at least a portion of the one phase shifted clock signal output by the selection circuit and outputs the sampled portion to form at least a part of an oscillator signal having a desired frequency.

公开(公告)号：EP1444783A2

公开(公告)日：2004-08-11

申请号：EP02773869.9

申请日：2002-10-23

Applicant: MOTOROLA, INC.

Inventor： JUAN, Jui-Kuo ,  STENGEL, Robert, E. ,  MARTIN, Frederick, L. ,  BOCKELMAN, David, E.

IPC: H03L1/00

CPC classification number: H03L7/16 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/14 ,  H03L2207/08

Abstract: A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.