Abstract:
A packet switching system (100) having a packet switch (140) employs an acknowledgment scheme in order assure the delivery of all fragments (310) comprising a fragmented data packet (300) to improve overall system throughput during the handling of packets (310) that require reassembly. When packet fragments (310) are lost, corrupted or otherwise unintelligible to a receiving device (92, 94), the acknowledgment scheme permits retransmission of the missing data. In addition, a second acknowledgment signal is scheduled by system processing resources (110) in order to verify the successful delivery of all retransmitted data.
Abstract:
A packet transmission system (100) for reducing request traffic contention and the likelihood of resource misallocation includes a communications controller (110) and a plurality of remote requesting units (112) requesting packet transmission services. In response to receipt of a request (302), the controller (110) transmits a grant (306) to a requesting unit (112) when packet transmission resources (304 and 310) are available or a request acknowledgment (306) when packet transmission resources (304 and 310) are unavailable. Each remote unit (112) comprises apparatus structure and method steps for transmitting requests (302) to the controller (110) and starting a first timer having an interval (T) determined as a function of a number (Q) of outstanding requests (302). Upon receipt of an acknowledgment (306), the remote unit (112) starts a second timer having an interval (T1) longer than the inverval (T). Upon expiration of either the first timer or the second timer, the remote unit (112) will then and only then transmit a duplicate request (302). By limiting the number of duplicate requests transmitted by a remote unit (112), the present invention operates to reduce request traffic contention and the likelihood of resource misallocation.
Abstract:
A common communication controller (17) is linked to a plurality of peripheral devices (28) by a network interface bus (26). Packets containing information is communicated between the controller and the peripherals over the bus which consists of a parallel packet bus and a plurality of control lines utilized to implement a communication protocol which increases the efficiencies of packet communications by the utilization of additional direct command lines between the communications controller (17) and peripherals (28).
Abstract:
A method and apparatus for preserving the sequential relationship of a plurality of data packets (310) generated by separate source devices (14) and ordered as a data stream (300), despite transmission over radio channels which introduce ordering errors comprises method steps and apparatus structure for identifying at a first terminal, data packets from within the data stream as a function of source, generating data packet sequence information for identified data packets, storing values corresponding to data packet sequence numbers as function of source and transmitting data packets, source device identity and packet sequence information to a second terminal having first terminal source device and data packet sequence information. Upon receipt of a first terminal transmission, the second terminal retrieves from second terminal memory, first terminal data packet sequence information and compares the stored data packet sequence information with received data packet sequence information. As a function of the comparison, received data packets are forwarded to an appropriate application for further processing when sequence information sequence numbers compared and stored in an order determined by the sequence information when the sequence numbers do not compare.
Abstract:
In this invention a hierarchical addressing technique is employed in a packet communications system to enhance flexibility in handling packet information. This method permits packet message data (Fig. 3) and certain packet control data (Fig. 3) to be stored in memory locations (32, 34) without having to be duplicated at a different memory location prior to transmission of the packet. This method is preferably employed in a ring configuration in which a series of packets have addressing mechanisms which points sequentially to each other to form a ring of packets.
Abstract:
Une architecture d'interface d'un réseau pour un commutateur de paquets/paquets rapides est décrite. Cet architecture prévoit la combinaison à la fois d'une voix et de données dans un seul commutateur, à l'aide d'une structure de paquets commune. Elle permet l'affectation dynamique d'une largeur de bande basée sur le chargement du système. Cela inclut non seulement la largeur de bande se trouvant dans les zones de voie ou de données du bloc, mais aussi entre les parties de voie et de données. L'interface (105) du réseau est dotée d'un moyen (101) passant tous les paquets par l'intermédiaire de ladite interface (105) du réseau, ou permettant à des dispositifs de paquets de se transférer directement des paquets les uns entre les autres. L'affectation de la largeur de bande peut être changée facilement, puisque les mémoires de commande et de données sont synchronisées les unes par rapport aux autres. L'architecture permet, à l'aide d'un seul dispositif de commutation, de commander les paquets de données ainsi que l'affectation de la largeur de bande. Elle synchronise le transfert des données ainsi que l'affectation de la largeur de bande de bus. La commande des dispositifs de paquets peut être effectuée à un débit binaire très élevée tel que 40 Mbps. Elle permet à des dispositifs de paquets de transférer directement des paquets. Elle permet une réaffectation facile de largeur de bande par l'emploi des registres de base NI.
Abstract:
A method and apparatus for preserving the sequential relationship of a plurality of data packets (310) generated by separate source devices (14) and ordered as a data stream (300), despite transmission over radio channels which introduce ordering errors comprises method steps and apparatus structure for identifying at a first terminal, data packets from within the data stream as a function of source, generating data packet sequence information for identified data packets, storing values corresponding to data packet sequence numbers as function of source and transmitting data packets, source device identity and packet sequence information to a second terminal having first terminal source device and data packet sequence information. Upon receipt of a first terminal transmission, the second terminal retrieves from second terminal memory, first terminal data packet sequence information and compares the stored data packet sequence information with received data packet sequence information. As a function of the comparison, received data packets are forwarded to an appropriate application for further processing when sequence information sequence numbers compared and stored in an order determined by the sequence information when the sequence numbers do not compare.
Abstract:
A network interface architecture for a packet/fast packet switch is described. This architecture provides for the combination of both voice and data in a single switch using a common packet structure. It allows for the dynamic allocation of bandwidth based on system loading. This includes not only bandwidth within the voice or data areas of the frame, but also between the voice and data portions. The network interface (105) provides a means (101) of passing all packets through the Network Interface (105) or allowing the packet devices to directly transfer packets between one another. The bandwidth allocation can easily be changed because the control and data memories are synchronized to one another. The architecture allows for the data packets and the control of bandwidth allocation to be controlled by a single switching device. It synchronizes the transfer of the data and the allocation of bus bandwidth. The control of the packet devices can be controlled at a very high bit rate such as 40 Mbps. It allows packet devices to directly transfer packets. It allows for easy re-allocation of bandwidth through the use of the NI Base Registers.