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公开(公告)号：DE69610004D1
公开(公告)日：2000-10-05
申请号：DE69610004
申请日：1996-03-06
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: In a high-power transmitter, an input complex signal is multiplied in a complex multiplier by control signals. The output complex signal from the multiplier is converted to a high frequency signal and amplified by a power amplifier for transmission. The amplitude of the input complex signal is detected to access a memory where amplitude and phase correction values are stored. During a read mode of the memory, a set of amplitude and phase correction values is specified by the detected amplitude and supplied to the complex amplifier as the control signals. During a write mode of the memory, a set of amplitude and phase correction values is specified by a delayed version of the detected amplitude and rewritten with a set of new amplitude and phase correction values. The amplified high frequency signal is down-converted to a low frequency complex signal. The nonlinearity of the power amplifier is determined from a delayed version of the input complex signal and the down-converted complex signal and the new amplitude and phase correction values are produced from the detected nonlineariry and delayed versions of the amplitude and phase correction values which were supplied to the complex multiplier. At intervals, the memory is switched from the read mode to the write mode for updating its contents.
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公开(公告)号：DE69132309D1
公开(公告)日：2000-08-17
申请号：DE69132309
申请日：1991-10-25
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H03L7/099 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/233
Abstract: A digital output of a quasi-coherent detection circuit (2) is M-th power multiplied and then processed by a set of digital filters to generate signals for coherent detection and clock interpolation. The digital output of the quasi-coherent detection circuit (2) is also fed, through a delay circuit (19), to coherent detection circuit which in turn processes the digital output of the quasi-coherent detection circuit, using the coherent detection signal. Timing error information indicative of the difference between phases of an interpolated clock and the interpolation signal determines the weighting factor of data interpolation channel filter (18) which in turn interpolate and output coherent-detected data signal.
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公开(公告)号：DE69216972T2
公开(公告)日：1997-09-04
申请号：DE69216972
申请日：1992-09-29
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
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公开(公告)号：DE69124904T2
公开(公告)日：1997-06-19
申请号：DE69124904
申请日：1991-10-04
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: A first clock signal of f1 in frequency is converted into a second clock signal having a frequency of f2 = n/m f1. The first clock signal is converted by a tank circuit (12) and a converter (13) into an R-bit first phase signal ( theta 1) indicating the phase of the first clock signal. The first phase signal is multiplied by n (mod 2 ) by a multiplier into a second phase signal ( theta 3). The second phase signal is supplied to a digital phase-locked loop (PIL) (3) consisting of a subtractor (15), a low-pass filter (LPF) (16), a numerically controlled oscillator (NCO) (17) and a multiplier (18). The multiplier in the digital PIL (3) multiplies by m (mod 2 ) a third phase signal, indicating the phase of a second clock signal which is the output of the NCO (17), to generate a fourth phase signal. The subtractor (15) generates a signal representing the phase error between the second and fourth phase signals. This phase error signal is filtered by the LPF (16) to control the oscillating phase of the NCO (17). A clock generating circuit generates, on the basic of the third phase, signal, the second clock signal.
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公开(公告)号：CA2079531C
公开(公告)日：1996-12-10
申请号：CA2079531
申请日：1992-09-30
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H03H17/08 , H04L27/00 , H04L27/22 , H04L27/227 , H04L27/233 , H03D3/02
Abstract: In a phase divider, a complex signal containing a sequence of samples of real and imaginary values is limited to a unit amplitude and multiplied by a first complex multiplier with a first feedback complex signal, the output the multiplier being fed through a loop filter to a second complex multiplier where the signal is multiplied with a second feedback complex signal. The output of the second multiplier is limited to a unit amplitude, delayed by a sample interval and applied to the second complex multiplier as the second feedback complex signal. The first feedback complex signal is derived by a circuit that raises the frequency the delayed signal by a desired factor.
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Patent Agency Ranking
公开(公告)号：CA2054247C
公开(公告)日：1996-05-21
申请号：CA2054247
申请日：1991-10-25
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04L27/227 , H03L7/099 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/233 , H03D3/00
Abstract: A digital output of a quasi-coherent detection circuit is M-th power multiplied and then processed by a set of digital filters to generate signals for coherent detection and clock interpolation. The digital output of the quasicoherent detection circuit is also fed, through a delay circuit, to coherent detection circuit which in turn processes the digital output of the quasi-coherent detection circuit, using the coherent detection signal. Timing error information indicative of the difference between phases of an interpolated clock and the interpolation signal determines the weighting factor of data interpolation channel filter which in turn interpolate and output coherent-detected data signal.
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公开(公告)号：AU8561691A
公开(公告)日：1992-04-09
申请号：AU8561691
申请日：1991-10-04
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: A first clock signal of f1 in frequency is converted into a second clock signal having a frequency of f2 = n/m f1. The first clock signal is converted by a tank circuit (12) and a converter (13) into an R-bit first phase signal ( theta 1) indicating the phase of the first clock signal. The first phase signal is multiplied by n (mod 2 ) by a multiplier into a second phase signal ( theta 3). The second phase signal is supplied to a digital phase-locked loop (PIL) (3) consisting of a subtractor (15), a low-pass filter (LPF) (16), a numerically controlled oscillator (NCO) (17) and a multiplier (18). The multiplier in the digital PIL (3) multiplies by m (mod 2 ) a third phase signal, indicating the phase of a second clock signal which is the output of the NCO (17), to generate a fourth phase signal. The subtractor (15) generates a signal representing the phase error between the second and fourth phase signals. This phase error signal is filtered by the LPF (16) to control the oscillating phase of the NCO (17). A clock generating circuit generates, on the basic of the third phase, signal, the second clock signal.
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公开(公告)号：AU7730491A
公开(公告)日：1991-11-28
申请号：AU7730491
申请日：1991-05-23
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
Abstract: In a phase-lock loop device for phase locking a device input signal (11) representing a first complex number and having a device input phase which should be locked into a locked phase, a first complex multiplier (14) calculates a first product of the first complex number and a first conjugate complex number to produce a first complex product signal. The first conjugate complex number is represented by a first conjugate signal which is produced by delaying and processing the device input signal. A second complex multiplier (18) calculates a second product of a phase processed signal and a multiplier input signal to produce a second complex product signal. The phase processed signal is produced by filtering and processing the first complex product signal. The multiplier input signal is produced by delaying and limiting the second complex product signal. A third complex multiplier (22) calculates a third product of the first complex number and a second conjugate complex number to produce a third complex product signal. The second conjugate complex number is represented by a second conjugate signal which is produced by processing the second complex product signal. A fourth complex multiplier (24) calculates a fourth product of the second complex product signal and a filtered signal to produce a fourth complex product signal having the locked phase. The filtered signal is produced by filtering the third complex product signal.
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公开(公告)号：CA1198181A
公开(公告)日：1985-12-17
申请号：CA426153
申请日：1983-04-19
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H04B1/26 , H03L7/10 , H03L7/113 , H04L27/227
Abstract: A phase synchronizing circuit which has an extended pull-in range compared with the conventional phaselock loop is disclosed. The conventional phaselock loop comprises a voltage controlled oscillator for generating an output signal in response to a control voltage, a phase comparator for phasecomparing the output signal from the voltage controlled oscillator with a first signal to provide a second signal, and a loop filter for smoothing the second signal to provide the control voltage. In addition to these components the inventive circuit includes a phase shifter which phase-shifts the output signal by (.pi./2) + n.pi. (n being an integer) to provide a third signal. A first mixer is provided for mixing the third signal with an input signal to provide a fourth signal. A low-pass filter selects a low frequency component out of the fourth signal and provides a fifth signal whose phase is delayed in correspondence with the frequency difference between the input and output signals. A second mixer is provided for mixing the fifth signal with the input signal to provide the first signal.
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公开(公告)号：DE69211468T2
公开(公告)日：1996-10-24
申请号：DE69211468
申请日：1992-09-30
Applicant: NEC CORP
Inventor： ICHIYOSHI OSAMU
IPC: H03H17/08 , H04L27/00 , H04L27/22 , H04L27/227 , H04L27/233
Abstract: In a phase divider, a complex signal containing a sequence of samples of real and imaginary values is limited to a unit amplitude and multiplied by a first complex multiplier with a first feedback complex signal, the output the multiplier being fed through a loop filter to a second complex multiplier where the signal is multiplied with a second feedback complex signal. The output of the second multiplier is limited to a unit amplitude, delayed by a sample interval and applied to the second complex multiplier as the second feedback complex signal. The first feedback complex signal is derived by a circuit that raises the frequency the delayed signal by a desired factor.
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