公开(公告)号：JPS62267656A

公开(公告)日：1987-11-20

申请号：JP11289386

申请日：1986-05-16

Applicant: NEC CORP

Inventor： KURIYAMA TOSHIHIDE

IPC: G01N27/414 ,  G01N27/00 ,  G01N27/30 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE:To prevent an Si nitride film from being deteriorated, and to exactly attain an insulation, by providing Al which becomes the electrode of a semiconductor ion sensor, on the Si nitride film through an Si oxide film. CONSTITUTION:On a sapphire substrate 1, p-type Si 2, source and drain areas 3, 4 of high impurity density n-type Si, and an earth area 5 of high impurity density p-type Si are formed, thereafter, an Si oxide film 6 which becomes the insulating gate film of an FET is formed, on which an Si nitride film 7 is vapor-deposited. Subsequently, an Si oxide film 8 for protecting the film 7 is formed, thereafter, a contact hole is bored, an Al film 9 is vapor-deposited, and by etching it, an electrode 9a is formed. Next, the Si oxide film 8 existing in an area containing a sensor part is eliminated by etching. In such way, the deterioration of the Si nitride film 7 which works as an ion sensitive film and insulating film can be prevented, and the insulating property is improved.

公开(公告)号：JPS62213761A

公开(公告)日：1987-09-19

申请号：JP5754286

申请日：1986-03-14

Applicant: NEC CORP

Inventor： KURIYAMA TOSHIHIDE

IPC: A61M1/36

公开(公告)号：JPS62135760A

公开(公告)日：1987-06-18

申请号：JP27837785

申请日：1985-12-10

Applicant: NEC CORP

Inventor： KURIYAMA TOSHIHIDE

IPC: G01N27/414 ,  G01N27/30

Abstract: PURPOSE:To obtain a sensor which permits mass production at a low cost by sticking a semiconductor wafer provided with an ISFET (semiconductor field effect type ion sensor) to an insulator wafer, further providing grooves arriving at the insulator wafer from the front side of the semiconductor wafer and filling the grooves with a water-resistant resin for insulation. CONSTITUTION:An impurity is diffused into the P-type silicon wafer 1 to form N-type regions 2, 3 of a high impurity concn. and a P-type region 4 of a high impurity concn. and thereafter a silicon oxide film 5 and a silicon nitride film 6 are formed thereon to make the ISFET in the wafer. The glass wafer 7 contg. alkali metal ions is stuck to the rear surface. The grooves 9 arriving at least at the wafer 7 from the front side of the wafer 2 are provided and a photosensitive resin 8 is coated on the surface. The chip-shaped ISFET obtd. by dicing the groove parts is peripherally enclosed by the insulator and is, therefore, already electrically insulated. The sensor is completed simply by connecting lead wires thereto.

公开(公告)号：JPS6239756A

公开(公告)日：1987-02-20

申请号：JP17961585

申请日：1985-08-14

Applicant: NEC CORP

Inventor： KURIYAMA TOSHIHIDE

IPC: G01N27/414 ,  G01N27/30

Abstract: PURPOSE:To obtain a minute semiconductor multi-biosensor, by providing a semiconductor electric field effect type ion sensor having a plurality of biologically related substances provided to the surface thereof and MOSFET tone end part of an insulating substrate so as to form a pair. CONSTITUTION:Plural pairs of semiconductor electric field effect type ion sensors (ISFETs) and MOSFETs are formed to one end of the monocrystalline silicon film on an elongated sapphire substrate 1 and the source regions of ISFETs and the drain regions MOSFETs form a common region. A plurality of ISFETs have a common drain and this drain region is extended to the other end of the substrate 1 to form a metal electrode 24 while a plurality of MOSFETs have a common source regions and this source region is extended to the other end of the substrate 1 to form a metal electrode 22. Further, the gate electrodes of MOSFETs are respectively covered with an insulator and extended to the other end of the substrate 1 to form metal electrodes 20. Be cause the drain region is common and also the source regions of respective ISFETs are common even if a plurality of ISFETs are integrated on one chip, an element area does not largely increase.

公开(公告)号：JPS61133853A

公开(公告)日：1986-06-21

申请号：JP25666984

申请日：1984-12-05

Applicant: Nec Corp

Inventor： KAWANA YOSHIE ,  KIMURA JUN ,  KURIYAMA TOSHIHIDE

IPC: C12Q1/00 ,  G01N27/30 ,  G01N27/414

CPC classification number: C12Q1/001 ,  G01N27/4145

Abstract: PURPOSE:To detect the concentration of several chemical substances in a sample solution simultaneously with a high sensitivity, by providing an FE type ion sensor having an enzyme immobilized membrane on the surface of an insulation substrate while an electrode having an enzyme immobilized membrane is provided on the other surface thereof. CONSTITUTION:This composite type enzyme electrode is made up of two ion sensitive FETs (ISFET) and two kinds of enzyme immobilized membranes provided on the top surface of a sapphire substrate insulator. An FE type ion sensor is made up of a p-type silicon substrate layer 2, an n-type high impurities density source region 3, an n-type high impurities density drain region 4, a p-type high impurities density earth region, a silicon oxide film 6, a silicon nitride film 7 and an ion sensitive film. Two precious metal electrodes 10 and 11 are provided on the undersurface of the substrate 1 and a second enzyme immobilized membrane is formed on the surface of one electrode 11. When measuring urea and glucolse, a urease immobilized membrane and a glucose oxidase immobilized membrane are used for the first and second enzyme immobilized membranes respectively.

Abstract translation: 目的：为了在高灵敏度的同时检测样品溶液中的几种化学物质的浓度，通过在绝缘衬底的表面上提供具有酶固定膜的FE型离子传感器，同时将具有酶固定膜的电极设置在 其另一个表面。 构成：该复合型酶电极由两个离子敏感FET（ISFET）和设置在蓝宝石衬底绝缘子顶表面上的两种酶固定膜组成。 FE型离子传感器由p型硅衬底层2，n型高杂质浓度源区3，n型高杂质浓度漏极区4，p型高杂质密度接地区构成， 氧化硅膜6，氮化硅膜7和离子敏感膜。 在基板1的下表面上设置两个贵金属电极10和11，并且在一个电极11的表面上形成第二酶固定膜。当测量尿素和葡萄糖时，使用固定有脲酶的膜和固定有葡萄糖氧化酶的膜 分别用于第一和第二酶固定膜。

公开(公告)号：JPS6188136A

公开(公告)日：1986-05-06

申请号：JP20916684

申请日：1984-10-05

Applicant: Nec Corp

Inventor： KURIYAMA TOSHIHIDE ,  KIMURA JUN ,  KAWANA YOSHIE

IPC: C12Q1/00 ,  G01N27/00 ,  G01N27/414 ,  G01N27/30

CPC classification number: C12Q1/001 ,  G01N27/4145

Abstract: PURPOSE:To form enzyme immobilizing films which are different from each other on the same chip by removing part of the photoresist coated on a semiconductor wafer then coating a protein soln. thereon and dissolving the photoresist. CONSTITUTION:The photoresist film 6 soluble in acetone is spin-coated on the front of a wafer constituted by forming semiconductor field effect type ion sensors ISFETs by using an island-shaped silicon layer on the front of a sapphire substrate 1 and depositing gold 10 by evaporation on the rear. The photoresist film 6 on the surface to be provided with the enzyme immobilizing film 9 is thereafter removed by photolithography using a photomask. A protein soln. contg. the 1st enzyme and crosslinking agent is then spin-coated to form an urease immobilizing film 7. The water is then immersed in acetone to dissolve the photoresist 6 and at the same time to remove the urease immobilizing film coated thereon. A glucose immobilizing film 9 is also formed by repeating the similar stage.

Abstract translation: 目的：通过除去涂覆在半导体晶片上的部分光刻胶，形成蛋白质溶胶，形成在同一芯片上彼此不同的酶固定膜。 在其上并溶解光致抗蚀剂。 构成：可溶于丙酮的光致抗蚀剂膜6通过在蓝宝石衬底1的前面使用岛状硅层形成半导体场效应型离子传感器ISFET而形成的晶片的前面旋涂，并通过 后方蒸发。 然后通过使用光掩模的光刻法去除设置有酶固定膜9的表面上的光致抗蚀剂膜6。 蛋白质溶胶 对比 然后旋涂第一酶和交联剂以形成脲酶固定膜7.然后将水浸入丙酮中以溶解光致抗蚀剂6，同时除去其上涂覆的脲酶固定膜。 还通过重复类似的阶段形成葡萄糖固定膜9。

公开(公告)号：JP2006313555A

公开(公告)日：2006-11-16

申请号：JP2006162491

申请日：2006-06-12

Applicant: Nec Corp ,  日本電気株式会社

Inventor： SASAKI HIDEKI ,  HARADA TAKASHI ,  KURIYAMA TOSHIHIDE

IPC: G06F17/50 ,  H05K3/00

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus for supporting design of a printed board, which is provided with a design function to suppress electromagnetic radiation in a common mode from the printed board. SOLUTION: The apparatus for supporting design of the printed board, which uses an information processor, includes a means for provisionally placing electronic components on the printed board, a means for interconnecting the provisionally placed electronic components with a shortest route of wiring, and a means for re-placing the provisionally placed electronic components so as to minimize the length of the wirings of the interconnection in a long side direction of a ground plane. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于支持印刷电路板设计的装置，其具有设计功能以抑制来自印刷电路板的共模的电磁辐射。 解决方案：用于支持使用信息处理器的印刷电路板的设计的装置包括用于将电子部件临时放置在印刷电路板上的装置，用于将临时放置的电子部件与最短布线布线相互连接的装置， 以及用于重新放置临时放置的电子部件的装置，以便使接地平面的长边方向上的互连的布线的长度最小化。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2002366600A

公开(公告)日：2002-12-20

申请号：JP2001176947

申请日：2001-06-12

Applicant: Nec Corp ,  日本電気株式会社

Inventor： HARADA TAKASHI ,  YAGUCHI TAKAHIRO ,  WAKUI AKIRA ,  ETANI SEIJI ,  SASAKI HIDEKI ,  KURIYAMA TOSHIHIDE

IPC: G06F17/50 ,  H05K3/00

Abstract: PROBLEM TO BE SOLVED: To provide a supporting device, a method and a program for design of a printed circuit board for suppressing radiation of unwanted electromagnetic waves regarding wiring between a power plane and a ground plane.
SOLUTION: The supporting device for design of a printed circuit board is provided with a means 2 to input printed circuit board layout information comprising signal wiring, power plane structure, ground plane structure, mounting positions of active elements such as an LSI, IC and passive elements such as a decoupling capacitor, a means 3 to discriminate the signal wiring, the power plane and the ground plane from the inputted information, a means 4 to select prescribed signal wiring and to discriminate whether or not the signal wiring is wired in an internal layer sandwiched between the power plane and the ground plane and a means 5 to display a discrimination result. The radiation of unwanted electromagnetic wave is suppressed by specifying the signal wiring sandwiched between the power plane and the ground plane to be a factor of the radiation of the unwanted electromagnetic waves at high level.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供一种用于设计用于抑制关于电力平面和接地平面之间的布线的不期望的电磁波的辐射的印刷电路板的支撑装置，方法和程序。 解决方案：印刷电路板设计用支撑装置设置有输入印刷电路板布局信息的装置2，包括信号布线，电源平面结构，接地平面结构，有源元件如LSI，IC和被动的安装位置 诸如去耦电容器的元件，用于从输入的信息中识别信号布线，电源平面和接地层的装置3，选择规定的信号布线的装置4，以及鉴别信号布线是否在内部布线 夹在电源平面和接地平面之间的层，以及显示辨别结果的装置5。 通过将夹在电源平面和接地面之间的信号布线指定为高电平的不需要的电磁波的辐射的因素来抑制不需要的电磁波的辐射。

公开(公告)号：JP2002353904A

公开(公告)日：2002-12-06

申请号：JP2001153768

申请日：2001-05-23

Applicant: NEC CORP

Inventor： SASAKI HIDEKI ,  KURIYAMA TOSHIHIDE

IPC: H05K9/00 ,  G06F1/18 ,  H04B15/02 ,  H05K1/02 ,  H05K1/14 ,  H05K3/36

Abstract: PROBLEM TO BE SOLVED: To prevent ground structure, with which first and second ground planes are connected by a connector, from generating strong electromagnetic fields, with which radio communication is interfered. SOLUTION: Since the edge of a second ground plane 15 opposite to a connector 14 is connected to a first ground plane 11 by a resistance connecting means 41, Q value of resonance in the ground structure can be lowered by the resistance connecting means 41 and the strong electromagnetic field can be prevented from being generated by the electromagnetic field of a data processing circuit. Especially, when the resistance value of the resistance connecting means 41 is identical to the characteristic impedance of the ground structure, since the ground structure is matched and terminated, the electromagnetic field can be surely prevented from being generated by resonance.

公开(公告)号：JP2002314452A

公开(公告)日：2002-10-25

申请号：JP2001112961

申请日：2001-04-11

Applicant: NEC CORP ,  NEC ACCESS TECHNICA LTD

Inventor： SASAKI HIDEKI ,  IMAZATO MASAHARU ,  MURAMATSU YUJI ,  KAKU TOSHIO ,  MURAMATSU HIDENORI ,  KURIYAMA TOSHIHIDE ,  YOSHINAGA KOJI

IPC: H05K1/14 ,  H01Q1/22 ,  H01Q9/04 ,  H04B1/38 ,  H04B1/3822 ,  H04B15/00 ,  H05K1/16

Abstract: PROBLEM TO BE SOLVED: To provide a data processing terminal that the 2nd ground plane of a slave circuit board does not generate interference electromagnetic field to wireless communication. SOLUTION: The 2nd ground plane 15 of nearly a rectangular shape is connected to a 1st ground plane 11 on which a data processing circuit is mounted and a wireless communication circuit 12 makes wireless communication with a communication wavelength λ. Part of the 2nd ground plane 15 from a ground connection means 14 at a consecutive edge of the plane 15 to a ground connection means 33 acts like an antenna, and since the largest interval (a) of a plurality of ground connection means 14, 33 at the consecutive edge of the 2nd ground plane 15 satisfies a relation of 'a