公开(公告)号：DE69422220D1

公开(公告)日：2000-01-27

申请号：DE69422220

申请日：1994-05-25

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: G11C11/409 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/094

Abstract: In an output circuit having first and second MOS transistors (Q1, Q2) in series between a first power supply line (Vcc, Vcc1) and a second power supply line (Vss1, Vss), and a third MOS transistor (Q3), the gates of the first and second transistors are connected to first and second input nodes, respectively, and an output node is provided between the first and second MOS transistors. The third MOS transistor is connected between one of the input nodes and the output node. The gate of the third MOS transistor is connected to a third power supply line (Vss2, Vcc2).

公开(公告)号：DE69407497T2

公开(公告)日：1998-07-23

申请号：DE69407497

申请日：1994-06-28

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H02H9/04

Abstract: A protective system (16) incorporated in a semiconductor integrated circuit device has a shared discharging line (16a) and a plurality of protective circuits (16c-16h) each having a diode (D) and a lateral bipolar transistor (CL) coupled between an associated pad (15c/12a/15i/14c/15k) and the shared discharging line (16a), and surge voltage applied to the pad is discharged through the associated protective circuit to the shared discharging line so that a main circuit (12/13) is not destroyed by the surge voltage.

公开(公告)号：DE69407497D1

公开(公告)日：1998-02-05

申请号：DE69407497

申请日：1994-06-28

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H02H9/04

Abstract: A protective system (16) incorporated in a semiconductor integrated circuit device has a shared discharging line (16a) and a plurality of protective circuits (16c-16h) each having a diode (D) and a lateral bipolar transistor (CL) coupled between an associated pad (15c/12a/15i/14c/15k) and the shared discharging line (16a), and surge voltage applied to the pad is discharged through the associated protective circuit to the shared discharging line so that a main circuit (12/13) is not destroyed by the surge voltage.

公开(公告)号：DE69106231D1

公开(公告)日：1995-02-09

申请号：DE69106231

申请日：1991-06-18

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A memory cell comprising a MOSFET formed on a principle surface of a semiconductor substrate and an information storage capacitor having a storage electrode formed in or on the substrate so as to contact with a drain region of the MOSFET, and a capacitor electrode formed adjacent to the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. The storage electrode is connected to the drain region of the MOSFET through a thin barrier layer which is formed between the drain region and the storage electrode region so as to prevent impurities in the storage electrode from being diffused into the drain region.

公开(公告)号：JP2005321292A

公开(公告)日：2005-11-17

申请号：JP2004139390

申请日：2004-05-10

Applicant: Nec Corp ,  日本電気株式会社

Inventor： TSUKAGOSHI TSUNEO ,  NARITA KAORU ,  KURIYAMA TOSHIHIDE ,  MASUDA NORIO

IPC: G01R31/26 ,  G01R31/00 ,  G01R31/28

Abstract: PROBLEM TO BE SOLVED: To solve a problem wherein the distribution of CDM discharge on an LSI chip cannot be measured.
SOLUTION: A detection probe 1, having a detector 1a at the tip thereof which can detect a magnetic field, is arranged on the LSI chip 11. A contact maker 2a of a charge/discharge probe 2 is in contact with a pad 11a on the LSI chip 11. The detection probe 1 can move in the XYZ directions with high precision. The detection probe 1 is connected to an oscilloscope 3. When a charge switch SW2 is closed, the LSI chip 11 is charged through the charge/discharge probe 2. When a discharge switch SW1 is closed then, charged electric charges are discharged to the LSI chip. The discharged current is detected with a resistor R1 of a discharged current detection section 7. The detected output is used as a trigger signal which captures an detection output of the probe 1 on the oscilloscope 3.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决问题：为了解决无法测量LSI芯片上CDM放电分布的问题。 解决方案：在LSI芯片11上设置检测探头1，其具有可检测磁场的尖端处的检测器1a。充电/放电探针2的触点制造器2a与焊盘接触 11a。检测探针1可以高精度地沿XYZ方向移动。 检测探头1连接到示波器3.当充电开关SW2闭合时，LSI芯片11通过充放电探针2充电。当放电开关SW1闭合时，充电的电荷被放电到LSI 芯片。 放电电流用放电电流检测部分7的电阻R1检测。所检测的输出用作在示波器3上捕获探针1的检测输出的触发信号。（C）2006， JPO＆NCIPI

公开(公告)号：JP2000133799A

公开(公告)日：2000-05-12

申请号：JP30289398

申请日：1998-10-23

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/332 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/60 ,  H01L27/02 ,  H01L27/088 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To surely prevent circuit elements from static damages, when an integrated circuit designed with finer patterns of less than 0.5 μm, particularly, when MOSLSI has a shallow trench isolation structure necessary for the finer patterns. SOLUTION: An N+ diffused layer 15, an N well 14, and a deep N-well 15 are formed in a position deeper than a shallow trench isolation region as an emitter diffused layer so that the discharge current of a bipolar transistor of a static protective element flows mainly vertically to the substrate surface. Then, an N+ diffused layer 17a and a P well 12 are formed on the substrate surface, as a collector and a base, respectively, of the bipolar transistor.

公开(公告)号：JPH08191132A

公开(公告)日：1996-07-23

申请号：JP231995

申请日：1995-01-11

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092

Abstract: PURPOSE: To increase the electrostatic breakdown strength of an MOS FET without making a dead space on an LSI chip. CONSTITUTION: An input terminal 1 and an input resistor 4, which is connected with this terminal 1 and consists of an N-type diffused layer, are provided on a P-type semiconductor substrate. Moreover, source diffused layers 51 and 52 of N-channel MOS FETs 101 and 102 for internal circuit are respectively connected with a grounding wire 3. As the FET 101 is within a short distance from the resistor 4, the connection of the wire 3 with the layer 51 is made via a tungsten silicide wiring 11, whereby a resistance is added to the FET 101 and the electrostatic breakdown strength of the FET 101 is increased. Thereby, a dead space in the vicinity of the resistor 4 is eliminated and a reduction in the area of a chip is made possible.

公开(公告)号：JPH07193193A

公开(公告)日：1995-07-28

申请号：JP14698593

申请日：1993-05-25

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/822 ,  G11C11/409 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/094 ,  H01L21/06

Abstract: PURPOSE:To prevent malfunction due to interference of a plurality of output circuits in the case of their presence. CONSTITUTION:Output transistors Q1, Q2 are connected directly between power VSS1 lines VCC, to provide a transistor Q3 which increaces the resistance to negative noise in output signal Dout. The ground potential VSS2 of the transistor Q3 is separated from the ground potential VSS1 of the output transistor Q2. Further, a voltage clamp element Q14 for preventing electrostatic breakdown of the transistor Q3 is connected between the gate and the source of the transistor Q3.

公开(公告)号：JPH07122558A

公开(公告)日：1995-05-12

申请号：JP29116293

申请日：1993-10-27

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L23/52 ,  H01L21/301 ,  H01L21/3205 ,  H01L23/528

Abstract: PURPOSE:To enhance heat dissipation effect of two layer scribe wiring structure by connecting two metal wiring layers thereof directly with a semiconductor substrate thereby spreading the heat from each metal wiring layer to the semiconductor substrate. CONSTITUTION:Two Al wiring layers 5, 7 constituting a scribe wiring are interconnected through a contact CNT. Both Al wiring layers 5, 7 are connected directly with the P type impurity diffusion layer 3 of a semiconductor substrate 1. Since both Al wiring layers 5, 7 are connected with the semiconductor substrate 1, heat dissipation effect can be enhanced through thermal conduction.

公开(公告)号：JPH0473963A

公开(公告)日：1992-03-09

申请号：JP18775490

申请日：1990-07-16

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PURPOSE:To prevent the decrease in punch-through voltage by forming a diffused layer in an active region on both sides of a word electrode, forming a storage electrode isolated from the word electrode by insulator and extending in a trench, and forming a common electrode over the storage electrode covered with a dielectric film. CONSTITUTION:An isolation film 102 is formed in an area other than an active region on a semiconductor substrate 101, and a trench 113 is formed to divide the active region. There are provided a word electrode 104 covering the inner wall of the trench and extending vertically; an n-type diffused layers 106 forming source and drain regions on both sides of the word electrode; and a storage electrode 107 in contact with the ntype diffused layer 106 (source region). One end of the electrode 107 extends over the isolation film 102, and the other end extends over the word electrode 104 in the trench 113. Further, a contact hole 114 is provided to connect the n-type diffused layer (drain region) with a digit electrode extending perpendicularly to the word electrode.