公开(公告)号：WO2009093698A4

公开(公告)日：2009-12-10

申请号：PCT/JP2009051092

申请日：2009-01-23

Applicant: NEC CORP ,  NARITA KAORU

Inventor： NARITA KAORU

IPC: C01B31/02 ,  B05D7/24 ,  C09D5/00 ,  C09D7/12 ,  C09D201/00 ,  H01L21/336 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L51/0003 ,  B82Y10/00 ,  C08K3/041 ,  C09D5/24 ,  C09D7/70 ,  H01L51/0048 ,  H01L51/0541 ,  H01L51/0545

Abstract: A method for forming a uniform and dense carbon nanotube-dispersed film irrespective of the characteristics of the carbon nanotube-dispersed liquid and the type of substrate, and a method for manufacturing a semiconductor device having excellent electrical characteristics with less variation in characteristics are provided. The method for forming the carbon nanotube-dispersed film includes steps of coating a substrate (110) with a carbon nanotube-dispersed liquid containing carbon nanotubes (1101) dispersed in a solvent, cooling droplets (102) of the carbon nanotube-dispersed liquid to increase the viscosity of the solvent, evaporating the solvent to uniformly precipitate the carbon nanotubes (1101) and form a carbon nanotube coating film (1012), forming, on the carbon nanotube coating film (1012), a coating film of a carbon nanotube-dispersed liquid (1013) with higher carbon nanotube concentration, and evaporating the solvent from the coating film of carbon nanotube-dispersed liquid (1013) to form a film having dispersed carbon nanotubes (1022).

Abstract translation: 提供了形成均匀且致密的碳纳米管分散膜的方法，而不管碳纳米管分散液体的特性和基板的类型如何，以及具有优异的电特性，特性变化小的半导体器件的制造方法。 形成碳纳米管分散膜的方法包括以下步骤：用分散在溶剂中的含有碳纳米管（1101）的碳纳米管分散液涂布基板（110），将碳纳米管分散液体的液滴（102）冷却至 提高溶剂的粘度，蒸发溶剂以使碳纳米管（1101）均匀沉淀并形成碳纳米管涂膜（1012），在碳纳米管涂膜（1012）上形成碳纳米管 - 具有较高碳纳米管浓度的分散液（1013），并从碳纳米管分散液（1013）的涂膜蒸发溶剂，形成具有分散的碳纳米管（1022）的膜。

公开(公告)号：WO2007102597B1

公开(公告)日：2007-11-08

申请号：PCT/JP2007054621

申请日：2007-03-02

Applicant: NEC CORP ,  NEC ELECTRONICS CORP ,  KUSHTA TARAS ,  NARITA KAORU ,  KANEKO TOMOYUKI ,  OGOU SHIN-ICHI

Inventor： KUSHTA TARAS ,  NARITA KAORU ,  KANEKO TOMOYUKI ,  OGOU SHIN-ICHI

IPC: H05K3/46

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract translation: 根据一个实施例，形成多层衬底中的将通孔结构和平面传输线接合的宽带过渡作为信号通孔焊盘与布置在相同导体层上的平面传输线之间的中间连接。 过渡部分的横向尺寸等于一端的通孔焊盘直径和另一端的焊条宽度; 根据通过三维全波模拟获得的数字图，过渡的长度可以等于间隙孔在平面传输线方向上的特征尺寸或者被定义为在时域中提供最小过量感抗 。

公开(公告)号：DE69422220T2

公开(公告)日：2000-09-07

申请号：DE69422220

申请日：1994-05-25

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: G11C11/409 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/094

Abstract: In an output circuit having first and second MOS transistors (Q1, Q2) in series between a first power supply line (Vcc, Vcc1) and a second power supply line (Vss1, Vss), and a third MOS transistor (Q3), the gates of the first and second transistors are connected to first and second input nodes, respectively, and an output node is provided between the first and second MOS transistors. The third MOS transistor is connected between one of the input nodes and the output node. The gate of the third MOS transistor is connected to a third power supply line (Vss2, Vcc2).

公开(公告)号：DE69106231T2

公开(公告)日：1995-08-10

申请号：DE69106231

申请日：1991-06-18

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A memory cell comprising a MOSFET formed on a principle surface of a semiconductor substrate and an information storage capacitor having a storage electrode formed in or on the substrate so as to contact with a drain region of the MOSFET, and a capacitor electrode formed adjacent to the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. The storage electrode is connected to the drain region of the MOSFET through a thin barrier layer which is formed between the drain region and the storage electrode region so as to prevent impurities in the storage electrode from being diffused into the drain region.

公开(公告)号：DE69623509T2

公开(公告)日：2003-05-28

申请号：DE69623509

申请日：1996-01-11

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092

Abstract: An input terminal and an input protective resistor of an N-type diffusion layer connected thereto are provided on a P-type semiconductor substrate. First and second N-type MOS transistors for internal circuit are connected to a grounding wiring at respective source diffusion layers. The first MOS transistor is located at closer distance from the input protective resister than the second MOS transistor. The source diffusion layer of the first MOS transistor and the grounding wiring are connected via a high melting point metal layer wiring, such as a tungsten silicide or so forth to increase a resistance to improve electrostatic breakdown potential. Accordingly, the distance between the input protective resistor and the first MOS transistor can be made smaller to eliminate dead space around the input protective resistor to enable reduction of a chip area.

公开(公告)号：DE69018734T2

公开(公告)日：1995-10-26

申请号：DE69018734

申请日：1990-08-22

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/772

公开(公告)号：DE69018734D1

公开(公告)日：1995-05-24

申请号：DE69018734

申请日：1990-08-22

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/772

公开(公告)号：EP0632560B1

公开(公告)日：1997-12-29

申请号：EP94110025

申请日：1994-06-28

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/06 ,  H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0251

公开(公告)号：DE69623509D1

公开(公告)日：2002-10-17

申请号：DE69623509

申请日：1996-01-11

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: H01L21/8234 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H01L27/092

Abstract: An input terminal and an input protective resistor of an N-type diffusion layer connected thereto are provided on a P-type semiconductor substrate. First and second N-type MOS transistors for internal circuit are connected to a grounding wiring at respective source diffusion layers. The first MOS transistor is located at closer distance from the input protective resister than the second MOS transistor. The source diffusion layer of the first MOS transistor and the grounding wiring are connected via a high melting point metal layer wiring, such as a tungsten silicide or so forth to increase a resistance to improve electrostatic breakdown potential. Accordingly, the distance between the input protective resistor and the first MOS transistor can be made smaller to eliminate dead space around the input protective resistor to enable reduction of a chip area.

公开(公告)号：DE69422220D1

公开(公告)日：2000-01-27

申请号：DE69422220

申请日：1994-05-25

Applicant: NEC CORP

Inventor： NARITA KAORU

IPC: G11C11/409 ,  H01L21/8234 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/78 ,  H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/094

Abstract: In an output circuit having first and second MOS transistors (Q1, Q2) in series between a first power supply line (Vcc, Vcc1) and a second power supply line (Vss1, Vss), and a third MOS transistor (Q3), the gates of the first and second transistors are connected to first and second input nodes, respectively, and an output node is provided between the first and second MOS transistors. The third MOS transistor is connected between one of the input nodes and the output node. The gate of the third MOS transistor is connected to a third power supply line (Vss2, Vcc2).