公开(公告)号：JPH01303575A

公开(公告)日：1989-12-07

申请号：JP13380588

申请日：1988-05-31

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06T1/20

Abstract: PURPOSE:To process both a processor access and a data transmission access in parallel with each other by securing the 2-port constitution for a local memory, an input double buffer memory and an output double buffer memory respectively. CONSTITUTION:The processor modules 11 and 12 are prepared together with a 2-port input double buffer memory 15, a 2-port output double buffer memory 16, and 2-port local memories 13 and 14. Therefore the serial and parallel 2-port memories are used to those memories 13-16. Then the blocks are transferred among these memories at a high speed and the accesses given from the processors 11 and 12 can be processed in parallel with each other. The data are written into or read out of the memories 13 and 24 at the parallel port side in accordance with the value of the data received from the processors 11 and 12. Otherwise the high-speed transfer of data can be controlled between the memories 13/14 and the memories 15/16 with the instructions given from the processors 11 and 12. Thus the data input/output processing can be carried out with high efficiency and in terms of asynchronous pipelines.

公开(公告)号：JPH01205233A

公开(公告)日：1989-08-17

申请号：JP2873288

申请日：1988-02-12

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F15/82 ,  G06F9/44

Abstract: PURPOSE:To efficiently attain a composite operation by operating plural operations in a pipeline way for plural operands with a processor unit. CONSTITUTION:The title circuit is composed of an input control part 11, a link table memory 12, a function table memory 13, a data memory 14, a cue memory 15, a processing unit 16, an output control part 17 and a ring bus to connect these. At the time of initial setting, the progressing unit 16 executes plural operations in a pipeline way for plural operands 16 in accordance with the instruction set at the function table memory 13 and thus, a composite operation is executed. Thus, without increasing the number of the times of the turning of a ring, the efficiency can be improved.

公开(公告)号：JPS6442741A

公开(公告)日：1989-02-15

申请号：JP19814487

申请日：1987-08-10

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F15/173 ,  G06F9/44 ,  G06F15/16 ,  G06F15/82

Abstract: PURPOSE:To contrive to execute the processing at a high speed, and also, to softly cope with a complicated processing, as well, by using a memory in which two ports of a serial port and a parallel port can be inputted and outputted independently to and from a local memory and a main memory. CONSTITUTION:A first ring in which plural data flow processors 21-28 and an interface circuit 31 are connected by pipeline buses 201-209 of a single direction becomes a processor module 11 of one unit, and plural pieces of processor modules 11-14 are connected by pipeline buses 106-109 of a single direction through the interface circuit 31 and form a second ring. Also, this processor is constituted by containing a bidirectional system bus 110 to which each interface circuit 31, one 2-port main memory 19 and one host processor 10 are connected, and local memories 15-18 of 2 ports which are connected to the interface circuit 31 by a parallel input/output port, connected to a main memory 19 by a serial input/output port, and provided on every processor module 11-14. In such a way, the processing can be executed at a high speed, and also, this processor can cope softly with a complicated processing, as well.

公开(公告)号：JPS62182844A

公开(公告)日：1987-08-11

申请号：JP2512786

申请日：1986-02-06

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F9/44 ,  G06F12/00 ,  G06F12/02 ,  G06F15/82

Abstract: PURPOSE:To attain the fast transfer of data between different address areas by obtaining both read and write addresses by calculation through a processor part in such a case where just the address calculation suffices with no change of the data value. CONSTITUTION:An interface circuit 302 serves as a switch that allocates the destinations of data to a memory circuit 301, processors 304-307 and a host processor 303 respectively with reference to the processor numbers of those destinations among the input data received from a processor 307. Then the data discrimination numbers, the memory address value, the data value and the control signal are outputted to the circuit 301 from the circuit 302. While the read data and the control signal is sent back to the circuit 302 from the circuit 301. The processor 303 performs the initialization an the execution control for processors 304-307, the circuit 301 and the circuit 302.

公开(公告)号：JPS61125042A

公开(公告)日：1986-06-12

申请号：JP24661984

申请日：1984-11-21

Applicant: Nec Corp

Inventor： IWASHITA MASAO

IPC: H05K3/00 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/66 ,  H01L21/82 ,  H01L23/52

CPC classification number: H01L21/82

Abstract: PURPOSE:To deal flexibly with a general treatment magnitude and a change of treatment method by dividing a region for wiring, by generating repeatedly the region address value in every stage and by controlling totally. CONSTITUTION:A numerical line generator 1 generates a start point end point coordinate value of every micro region in dividing a region NXN for wiring into micro regions nXn in detail. Both a start point and an end point of a pinpair for wiring in a pinpair memory list stored in a pinpair list memory 2 searches at first for a route about what is contained in every nXn micro region. A route searching circuit 4 reads out contents of a stored map memory storing an empty region at present. Referring to an information indicating an empty region written in the map memory and a wired route information written in the map memory, a route for new wiring is found out in a position on two-dimentional coordinate indicated by both a pinpair start point address and an end point address, and an empty region condition of the map memory is renewed.

Abstract translation: 目的：通过对布线区域进行划分，通过在每个阶段重复产生区域地址值，并进行全面控制，灵活处理一般处理量和改变处理方法。 构成：数字线生成器1在将区域NXN分割为微区域nXn时，生成每个微区域的起点终点坐标值。 针对存储在针air列表存储器2中的针灸存储器列表中的布线的起始点和终点，首先搜索关于每个nXn微区域中包含的内容的路线。 路径搜索电路4当前存储存储空区域的存储地图存储器的内容。 参考表示写入地图存储器中的空白区域的信息和写入映射存储器中的有线路由信息，在由两个起始点地址和 终点地址，地图存储器的空区域条件被更新。

公开(公告)号：JPS59205651A

公开(公告)日：1984-11-21

申请号：JP8038083

申请日：1983-05-09

Applicant: Nec Corp

Inventor： IWASHITA MASAO

IPC: G06F9/34 ,  G06F9/44 ,  G06F12/00 ,  G06F13/00 ,  G06F15/82

Abstract: PURPOSE: To obtain an address generating circuit which can be easily produced and used in several divided functions with a small hardware quantity with high regularity, by controlling the address of a data memory.
CONSTITUTION: An address control part 3 supplies the base and sizes 19W21 of the addresses read out of a parameter table 2, counter value reading signals 24W 25 of addresses, an instruction code 26, internal states 22W23, a data identification number 12 outputted from an input latch 1, the input data value 13 and an input data type number 14, respectively. Then the address value 27, a read/ write control signal 28 and an effective flag 29 are outputted to an output latch 4; while address counter values 15W16 and internal states 17W18 are outputted to a parameter table memory 2. A data flow processor divides a data memory to use functions for the queuing control of double input data value, the read/ write of the data memory, the generation of a numerical string, the qualification of data value and the transition of the data value, respectively. Then the address of the data memory is controlled.
COPYRIGHT: (C)1984,JPO&Japio

Abstract translation: 目的：通过控制数据存储器的地址，获得可以容易地以几个具有较小规模的硬件数量的分割功能产生和使用的地址产生电路。 构成：地址控制部分3提供从参数表2读出的地址的基地址和大小19-21，地址的计数器值读取信号24-25，指令代码26，内部状态22-23，数据标识 从输入锁存器1输出的数字12，输入数据值13和输入数据类型号14。 然后将地址值27，读/写控制信号28和有效标志29输出到输出锁存器4; 而地址计数器值15-16和内部状态17-18被输出到参数表存储器2.数据流处理器分配数据存储器以使用用于双输入数据值的排队控制的功能，数据的读/写 内存，数字字符串的生成，数据值的限定和数据值的转换。 然后控制数据存储器的地址。

公开(公告)号：JPH03100755A

公开(公告)日：1991-04-25

申请号：JP23861689

申请日：1989-09-13

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06N3/10 ,  G06F15/18 ,  G06N3/04

Abstract: PURPOSE:To perform the processing at a high speed by obtaining center processing results preliminarily transposed in respective processor modules to reduce the processing for special transposition and the number of times of data transfer at the time of divisional processing of plural processor modules. CONSTITUTION:Processings whose number is obtained by dividing b-number of intermadiate layers by (n) are assigned to processor modules 1 and 2, and partial charge of processings of networks of a-number of input layers and c- number of output layers coupled to them are taken by processor modules, and a partial sum of output layers is obtained by each of processor modules 1 and 2, and thereafter, data is collectively transferred to one shared memory 13 to obtain the total sum. The total sum and the error obtained from a teacher signal are collectively transferred as data to processor modules 1 and 2, and values of weights of networks coupled to n-number of intermediate layers are obtained by processor modules 1 and 2. Neural network recognition and learning processing are performed without transposition for weight it values of networks on the shared memory 13. Thus, the processing is performed at a high speed.

公开(公告)号：JPS62219042A

公开(公告)日：1987-09-26

申请号：JP6331086

申请日：1986-03-19

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F9/44 ,  G06F12/00

Abstract: PURPOSE:To perform processing at a high speed by providing a memory circuit with a data memory and a comparator and comparing the coordinate value in the depth direction stored in the data memory with a new coordinate value in the depth direction inputted from a data flow processor by the comparator to control whether contents of the data memory should be updated or not. CONSTITUTION:A comparator 34 compares conventional coordinate values read out from a data memory 33 with a new inputted coordinate value and outputs a comparison signal 52. The comparison signal 52 is inputted to a control part 35, and AND between this signal and a control signal 51 of a functional memory 32 is operated and is inputted to a register 36. The register 36 samples and holds a write signal 53 by the rise of a clock signal 44 and inputs it to the data memory 33 as a write signal 54 by the fall. The operation of the data memory 33 is controlled in the latter half of the clock signal by the value of the write signal 54, and the write operation is performed to update contents in the address of the memory if this value is '1', and the write operation is not performed to hold contents in the address of the memory as they are if it is '0'.

公开(公告)号：JPS6191737A

公开(公告)日：1986-05-09

申请号：JP21387584

申请日：1984-10-12

Applicant: Nec Corp

Inventor： IWASHITA MASAO

IPC: G06F7/00 ,  G04F10/00 ,  G04F10/04 ,  G06F9/44 ,  G06F11/34 ,  G06F15/82

Abstract: PURPOSE: To shorten a measurement time by counting the time only when a significance flag signal is '0', counting the number of significant data, and measuring the arithmetic processing time of the significant data on real-time basis.
CONSTITUTION: Initialization is performed and then when the significance flag signal 11 goes up to a logical level '0', a counter 3 is enabled to start counting up with the leading edge of a clock 26. The contents of the counter 3 show the number of clocks 3 after the significance flag signal 11 having the logic '0' appears, and its output signal 16 is latched in a register 4. Its output signal 17 indicates the number of clocks 26 from the 1st arrival to the final arrival of the significance flag signal 11 having the logic '0', and the arithmetic processing time is calculated.
COPYRIGHT: (C)1986,JPO&Japio

Abstract translation: 目的：通过计数显示标志信号为“0”的时间，计数有效数据的数量，并实时测量有效数据的运算处理时间，缩短测量时间。 构成：执行初始化，然后当有效标志信号11上升到逻辑电平“0”时，计数器3使能以与时钟26的前沿开始计数。计数器3的内容显示数字 出现具有逻辑“0”的有效标志信号11之后的时钟3，并且其输出信号16被锁存在寄存器4中。其输出信号17表示从第一到达到最终到达的时钟26的数量 具有逻辑“0”的标志信号11，并计算运算处理时间。

公开(公告)号：JPS59195746A

公开(公告)日：1984-11-06

申请号：JP7105783

申请日：1983-04-22

Applicant: Nec Corp

Inventor： IWASHITA MASAO

IPC: G06F15/82 ,  G06F9/44

Abstract: PURPOSE: To detect the end of a processing by changing partially or regularly the processing for a series of data and subjecting only the end part of, for example, picture data to a special processing or counting the number of already processed data.
CONSTITUTION: A data value 14 is preliminarily written in a parameter table memory 2 before the start of an operation processing. A read/write switching signal 13 is used as a switching signal at this time; and if its value is "1", write is performed. An input data identification number 40 is used as an address. The capacity of the table memory 2 is determined by the product between the number of input data identification numbers 40 and the sum of bit widths of individual fields of the table memory 2. An operation control part 4 performs a processing for read signals 15W18 from the table memory 2 to generate an output data identification number 39.
COPYRIGHT: (C)1984,JPO&Japio

Abstract translation: 目的：通过部分或定期更改一系列数据的处理来检测处理结束，仅对图像数据的结束部分进行特殊处理或计数已处理数据的数量。 构成：在开始操作处理之前，将数据值14预先写入参数表存储器2。 此时，读/写切换信号13用作切换信号; 并且如果其值为“1”，则执行写入。 输入数据识别号码40用作地址。 表存储器2的容量由输入数据识别号码40的数量与表存储器2的各个字段的位宽之和的乘积确定。操作控制部分4对读取信号15-18执行处理 从表存储器2产生输出数据标识号39。