公开(公告)号：DE3275139D1

公开(公告)日：1987-02-19

申请号：DE3275139

申请日：1982-10-22

Applicant: NEC CORP

Inventor： IWASHITA MASAO ,  TENMA TSUTOMU

IPC: G06F9/44

Abstract: A data processing machine for high speed processing especially of programs involving repeated executions of operational steps is disclosed, which comprises: A first memory for storing destination addresses of data; a second memory being accessed with the destination addresses output from said first memory and storing instructions therein; a third memory for receiving the data and holding it therein temporarily; a fourth memory allowing the data sent from said third memory to wait for another; an arithmetic means executing arithmetic operation in accordance with the instructions read out from said second memory; a bus for coupling said first memory, second memory, third memory, fourth memory and said arithmetic means into a ring shape; and a means for storing the destination addresses and the instruction transferred from the outside into said first and second memories, respectively. By this structure the arithmetic means and the first to fourth memories are formed in a pipe line mode, the instructions input through the interface part are stored in the second memory, and arithmetic processing for data flowing through the ringshaped bus is executed in the arithmetic means in accordance with instructions which are fetched from the second memory. The sequence of operations in the pipe line mode can be programmably controlled in accordance with the arranged instructions in the second memory.

公开(公告)号：JPH01205259A

公开(公告)日：1989-08-17

申请号：JP2872788

申请日：1988-02-12

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F15/17 ,  G06F13/38 ,  G06F15/16

Abstract: PURPOSE:To efficiently execute a data transfer by simultaneously copying the data of a shared memory to plural local memories by means of a transfer once in the data transfer between one shared memory and plural local memories. CONSTITUTION:The title circuit is composed of processor modules 1 and 2, a bus arbiter 3, and a shared image memory module 4 to have a shared image memory 13 as one shared memory. According to data transfer requests from processors 21 and 22, a batch data transfer is executed between one shared memory 13 and plural local memories 11 and 12. Consequently, the same contents can be simultaneously copied to plural local memories 11 and 12 by transferring once. Thus, the data transfer can be efficiently executed.

公开(公告)号：JPS6421670A

公开(公告)日：1989-01-25

申请号：JP17822287

申请日：1987-07-17

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F17/50

Abstract: PURPOSE:To speed up an arrangement exchange by obtaining the total sum of a shortest wiring length between the selecting parts of (m) pieces as an evaluation function, executing the arrangement exchange only when an evaluated value after the arrangement exchange goes to small and executing the computation of (m) factorial evaluation functions in parallel. CONSTITUTION:One part is respectively arranged to respective small areas shown by numbers 1-64 divided into the grid shape of 8X8. At first, the components of the (m) pieces, for example, the components of the areas 19, 30, 50 and 56 are selected at random out of the initially arranged parts and the evaluation function is obtained with the total sum of the shortest wiring length between the mutual components as the evaluation function. In comparison with the evaluation function value before the arrangement exchanging, only when the evaluation function value after the arrangement exchange goes to small, operation to execute the arrangement exchange is repeated, the evaluation function is made approximate to the minimum value. Furthermore, the computational processing of (m) factorial evaluation functions is executed in parallel. Thus, the arrangement exchange can be executed at high speed.

公开(公告)号：JPS6315367A

公开(公告)日：1988-01-22

申请号：JP15823786

申请日：1986-07-04

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F17/50

Abstract: PURPOSE:To heighten speed of processing by making parallel searching process for all cells of 1 wavefront in four directions, east, west, south, north in diffusion process. CONSTITUTION:Wavefront addresses near east, west, south, north are formed on the basis of real address of a map and map information is referred and renewed, and at the same time, processing of one time with the same label for the nearest adjoining map is made in parallel for all wavefronts in each direction of diffusion process of wave in four directions, east, west, south, north, of wavefront. For instance, search is made from four cells included in the wavefront for four nearest cells. Such search is made in order of directions north, west, south, east, and search is made in parallel in north direction from all wavefront cells by plural processors. Then, process is proceeded in west direction, south direction and east direction. Thus, by dividing processing by directions, collision of waves can be avoided. As processing in each direction can be made independently, it is not always necessary to make processing in order of east, west, south, north.

公开(公告)号：JPS61182136A

公开(公告)日：1986-08-14

申请号：JP2114185

申请日：1985-02-06

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F15/82 ,  G06F7/38 ,  G06F9/44

Abstract: PURPOSE:To process easily a data flow by supplying data and their identification numbers to rearrange these identification numbers are prescribed in the order of the data flows unified and also to deliver them. CONSTITUTION:A data value 101 and the data flow identification number 102 are latched by register 1. The number 102 controls a control part 4 in the form of a signal 105 to write or read the valve 101 on and out of a memory 2 or 3. A the same time, multiplexers 5-7 are controlled and rearranged. When the data consists of a high-order address, a low-order address and a data address, these addresses are recognized based on those data flow identification numbers. Thus the data if supplied disorderly can be rearranged and delivered at a time when they are arranged in order. Furthermore, an effective flag signal 115 is delivered to an external circuit to show the validity or invalidity of data.

公开(公告)号：JPS5936857A

公开(公告)日：1984-02-29

申请号：JP14720182

申请日：1982-08-25

Applicant: Nec Corp

Inventor： IWASHITA MASAO

IPC: G06F15/82 ,  G06F9/44

CPC classification number: G06F9/4436

Abstract: PURPOSE: To obtain a processor unit having both functions of operation and numeral generation with a same hardware by providing said unit with a multiplexer switching a bus from an input latch and the one from an output latch.
CONSTITUTION: External data are inputted to the input latch 1 from a queue memory 6 and latched by a clock pulse 21. An operation part 2 to execute logical operation or arithmetic operation executes the operation by using output data from the input latch 1 and that from the multiplexer 5. The input of the multiplexer 5 is supplied from the input latch 1 and the output latch 3. While referring a part of the data from the input latch 1, a control part 4 switches the multiplexer 5. In case of logical operation or arithmetic operation, the data from the input latch 1 are selected as the output of the multiplexer 5, and at the generation of a numeral, the data from the output latch 3 are selected by a control signal 18.
COPYRIGHT: (C)1984,JPO&Japio

Abstract translation: 目的：通过向所述单元提供从输入锁存器切换总线和从输出锁存器切换总线的多路复用器来获得具有相同硬件的操作和数字生成功能的处理器单元。 构成：外部数据从队列存储器6输入到输入锁存器1并由时钟脉冲21锁存。执行逻辑运算或算术运算的操作部分2通过使用来自输入锁存器1的输出数据执行该操作， 复用器5.多路转换器5的输入端从输入锁存器1和输出锁存器3提供。当参考输入锁存器1的一部分数据时，控制部分4切换多路复用器5.在逻辑运算的情况下 或算术运算，来自输入锁存器1的数据被选择作为多路复用器5的输出，并且在产生数字时，来自输出锁存器3的数据由控制信号18选择。

公开(公告)号：JPH01303525A

公开(公告)日：1989-12-07

申请号：JP13380488

申请日：1988-05-31

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F15/16 ,  G06F9/44 ,  G06F15/82

Abstract: PURPOSE:To prevent the overflow of a data queue memory by giving the higher priority to the reading of the data queue memory than the reading of a generator queue memory and sending the interim result back to the inlet of the generator queue memory. CONSTITUTION:No data is read out of a generator queue memory 3 as long as just a single piece of data to be read out remains in a data queue memory 4. Thus the memory 4 is read out first. In other words, the memory 4 has the higher priority than the memory 3 in a read mode. The data read out of the memory 3 are used for production of a piece of data within a computing element 6 and the number of produces series are decreased. Thus the operation is through when said decrease value is equal to 0. While the interim value, the increase value and the number of produced series are written again into the memory in case the decrease value is not equal to 0. Thus the decentralization of load is secured and the stable control of data quantity is facilitated.

公开(公告)号：JPS6315369A

公开(公告)日：1988-01-22

申请号：JP15823986

申请日：1986-07-04

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F17/50

Abstract: PURPOSE:To execute clearing process at high speed by making an objective area of clearing process rhombic basically. CONSTITUTION:A means that calculates (x', y') given by x'=(x+y), y'=(-x+y) from wavefront address, and finds out maximum value and minimum value (xmax, ymax), (xmin, ymin), (xmax', ymax'), (xmin', ymin') of (x, y), (x', y') for 1 pin pair, a means that refers to a cell designated by an address (x, y), makes diffusing process and labeling, and a means that makes back tracing process tracing the added label reversely and finding wiring route. Thereby, maximum and minimum values of a rhombic area is found for wavefront address simultaneously with diffusing process, and clearing process is applied to route information and label only in the extent enclosed by the area.

公开(公告)号：JPS6315368A

公开(公告)日：1988-01-22

申请号：JP15823886

申请日：1986-07-04

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06F17/50

Abstract: PURPOSE:To make high speed clearing process possible by making clearing process selectively for necessary bit by bit plane access. CONSTITUTION:Access by word address is processed by word unit such as the first time is (0, 0), (1, 0), (2, 0), (3, 0), the second time is (3, 1), (0, 1), (1, 1), (2, 1), the third time is (2, 2), (3, 2), (0, 2), (1, 2), the fourth time is (1, 3), (2, 3), (3, 3), (0, 3). Access for clearing by bit plane address clears (2, 0), (3, 0), (3, 3), (2, 2), (3, 2), (2, 3), (3, 3) which are lower second digit of 1 word. That is, (2, 0), (3, 1), (3, 2), (2, 3) is cleared in the first time, and (3, 0), (3, 1), (3, 2), (3, 3) is cleared in the second time. Thus, the number of times of processing is completed a half the number of times for all words.

公开(公告)号：JPS62134773A

公开(公告)日：1987-06-17

申请号：JP27545185

申请日：1985-12-06

Applicant: NEC CORP

Inventor： IWASHITA MASAO

IPC: G06T7/00

Abstract: PURPOSE:To derive an altitude difference with a high accuracy and at high speed even when the altitude difference is comparatively large, by forecasting an inclination by using a known altitude corresponding to an adjacent picture element, and executing the expansion and contraction of a search area by its forecasting value. CONSTITUTION:Two pieces of image data which become objects of a processing are stored in an image memory 308 through a control use computer 302 from a host personal computer 301. Plural pieces of pipeline processors 304-307 are programmable, and in accordance with the contents of the processing, a control code is initialized in advance from the host personal computer 301. The control use computer 302 shares in a start control of processor groups 304-307 or a part of the processing, and executes it. An interface circuit 303 switches as a time division and executes generation of an address of an image memory 308, a read-out/write control, and a transfer of a data to the processor groups 304-307 and the control computer 302.