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    Capacitor
    11.
    发明授权
    Capacitor 有权

    公开(公告)号：US09773618B2

    公开(公告)日：2017-09-26

    申请号：US14831964

    申请日：2015-08-21

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Tae Hwan Song

    IPC: H01G4/30 ,  H01G4/12 ,  H01G4/38 ,  H01G4/005 ,  H01G4/012 ,  H01G4/228

    CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/012 ,  H01G4/12 ,  H01G4/228 ,  H01G4/38

    Abstract: The present invention relates to a capacitor. The capacitor includes a substrate; a dielectric layer formed on the substrate; and an electrode layer comprising a first electrode layer and a second electrode layer formed on the dielectric layer, wherein the first electrode layer and the second electrode layer are separated from each other, and at least a portion of the first electrode layer and at least a portion of the second electrode layer are disposed on a same surface. With this configuration, applying the electricity becomes easy, and since the first and the second electrode layers function as the electrodes being charged with different polarity electrical charges respectively, manufacturing thereof becomes easy, and the structure thereof is simple.

    Micro Heater and Micro Sensor
    13.
    发明申请
    Micro Heater and Micro Sensor 审中-公开
    微加热器和微型传感器

    公开(公告)号：US20160370336A1

    公开(公告)日：2016-12-22

    申请号：US15181976

    申请日：2016-06-14

    Applicant: Point Engineering Co., Ltd.

    Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Sung Hyun Byun

    IPC: G01N33/00 ,  H05B3/03 ,  H05B3/24 ,  H05B1/02

    CPC classification number: G01N33/0027 ,  G01N27/121 ,  G01N27/128 ,  H05B1/0247 ,  H05B3/03 ,  H05B3/24

    Abstract: A micro heater includes a substrate and a heater electrode formed on the substrate. The substrate includes a plurality of pores formed to vertically extend through the substrate. A micro sensor includes a substrate, a sensor electrode formed on the substrate, and a heater electrode formed on the substrate. A protective layer may be used to protect any of the electrodes against oxidation. Any of the electrodes may be formed on a barrier layer positioned on the porous layer.

    Abstract translation: 微加热器包括形成在基板上的基板和加热电极。 衬底包括形成为垂直延伸穿过衬底的多个孔。 微型传感器包括基板，形成在基板上的传感器电极和形成在基板上的加热电极。 可以使用保护层来保护任何电极免受氧化。 任何电极可以形成在位于多孔层上的阻挡层上。

    Method for mounting a chip and chip package
    15.
    发明授权
    Method for mounting a chip and chip package 有权
    安装芯片和芯片封装的方法

    公开(公告)号：US09378986B2

    公开(公告)日：2016-06-28

    申请号：US14511353

    申请日：2014-10-10

    Applicant: Point Engineering Co., Ltd.

    Inventor： Bum Mo Ahn ,  Ki Myung Nam ,  Seung Ho Park

    IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48

    CPC classification number: H01L21/563 ,  H01L21/4825 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/562 ,  H01L24/11 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1134 ,  H01L2224/1183 ,  H01L2224/13144 ,  H01L2224/291 ,  H01L2224/32013 ,  H01L2224/32227 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83815 ,  H01L2224/92227 ,  H01L2924/12041 ,  H01L2924/15156 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

    Abstract: Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the. In addition, cracking due to the difference of thermal expansion coefficient between solder materials can be prevented by sealing the bonding portion of the chip using the solder materials. Further, since oxidation of the bonding portion is prevented by blocking the contact with the outside, the chip packaging process can be performed without an additional process of filling an inert gas into the internal space wherein the chip is mounted.

    Abstract translation: 提供了一种安装芯片的方法。 该方法包括：在衬底的内部方向上凹入地形成的空腔的一个表面上形成凸块; 执行压印工艺以平坦化凸块的表面; 在经过压印加工的凸块上涂覆焊料; 并且通过熔化焊料材料来接合芯片和凸块，其中在芯片的底部上形成电极部分或金属部分。 对于根据本发明的金属基板，其中包括垂直绝缘层，由于芯片的电极部分和基板的电极部分必须电连接，金属基板被接合到芯片的电极部分 使用另外形成在金属基板上的凸块，使得芯片中产生的热量可以快速转移到基板，并且可以降低芯片的结温，从而提高光效率。 此外，通过使用焊料材料密封芯片的接合部分，可以防止由于焊料材料之间的热膨胀系数的差异导致的破裂。 此外，由于通过阻挡与外部的接触来防止接合部的氧化，所以可以进行芯片封装处理，而不需要在安装芯片的内部空间中填充惰性气体的附加处理。

    Heat Sink for Chip Mounting Substrate and Method for Manufacturing the Same
    16.
    发明申请
    Heat Sink for Chip Mounting Substrate and Method for Manufacturing the Same 审中-公开
    散热片用于芯片安装基板及其制造方法

    公开(公告)号：US20150117035A1

    公开(公告)日：2015-04-30

    申请号：US14511357

    申请日：2014-10-10

    Applicant: Point Engineering Co., Ltd.

    Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Tae Hwan Song

    IPC: F21V29/70 ,  F21V19/00

    CPC classification number: F21V19/005 ,  F21V29/767 ,  F21Y2115/10 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

    Abstract: Provided is a heat sink for a chip mounting substrate in which a heat dissipation material is embedded. The heat sink includes: an accommodation portion configured to accommodate a substrate whereon a chip is mounted or to be mounted, and support or fix the accommodated substrate; and a heat dissipation portion configured to insulate the accommodated substrate, and dissipate heat generated from the substrate or the chip mounted on the substrate to an outside through a heat dissipation material contained in the heat dissipation portion. Accordingly, since the heat sink for a chip mounting substrate in which a heat dissipation material is embedded is manufactured by injection molding, a manufacturing process can be simplified. Further, since the heat sink of a single structure is used, a TIM bonding layer for bonding the substrate and the heat sink is not required, and an electrical insulating layer formed by anodizing an upper surface of the heat sink for electrical insulation between the substrate and the heat sink is not required, and thus the structure can be simplified.

    Abstract translation: 本发明提供一种嵌入散热材料的芯片安装基板用散热片。 散热器包括：容纳部分，其构造成容纳其中安装或要安装的芯片的基板，并且支撑或固定所容纳的基板; 以及散热部，其被配置为使所容纳的基板绝缘，并且通过包含在所述散热部中的散热材料将从所述基板或安装在所述基板上的所述芯片产生的热散发到外部。 因此，由于通过注射成型制造其中嵌入有散热材料的芯片安装基板的散热器，因此可以简化制造工艺。 此外，由于使用单一结构的散热器，不需要用于粘合基板和散热器的TIM接合层，并且通过阳极氧化散热器的上表面而形成的电绝缘层用于基板之间的电绝缘 并且不需要散热器，因此可以简化结构。

    Method for Mounting a Chip and Chip Package
    17.
    发明申请
    Method for Mounting a Chip and Chip Package 有权
    安装芯片和芯片封装的方法

    公开(公告)号：US20150102486A1

    公开(公告)日：2015-04-16

    申请号：US14511353

    申请日：2014-10-10

    Applicant: Point Engineering Co., Ltd.

    Inventor： Bum Mo Ahn ,  Ki Myung Nam ,  Seung Ho Park

    IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00

    CPC classification number: H01L21/563 ,  H01L21/4825 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/562 ,  H01L24/11 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/1134 ,  H01L2224/1183 ,  H01L2224/13144 ,  H01L2224/291 ,  H01L2224/32013 ,  H01L2224/32227 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83815 ,  H01L2224/92227 ,  H01L2924/12041 ,  H01L2924/15156 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

    Abstract: Provided is a method of mounting a chip. The method includes: forming a bump at one surface of a cavity formed concavely in an inner direction of a substrate; performing a coining process to flatten a surface of the bump; coating a solder material on the bump subjected to the coining process; and bonding a chip and the bump by melting the solder material, wherein an electrode portion or a metal portion is formed on a bottom of the chip. For a metal substrate according to the present invention, wherein a vertical insulating layer is included, since the electrode portion of the chip and the electrode portion of the substrate have to be electrically connected, the metal substrate is bonded to the electrode portion of the chip using the bump additionally formed on the metal substrate, so the heat generated in the chip can be rapidly transferred to the substrate, and the junction temperature of the chip can be decreased, thereby enhancing the light efficiency and the. In addition, cracking due to the difference of thermal expansion coefficient between solder materials can be prevented by sealing the bonding portion of the chip using the solder materials. Further, since oxidation of the bonding portion is prevented by blocking the contact with the outside, the chip packaging process can be performed without an additional process of filling an inert gas into the internal space wherein the chip is mounted.

    Abstract translation: 提供了一种安装芯片的方法。 该方法包括：在衬底的内部方向上凹入地形成的空腔的一个表面上形成凸块; 执行压印工艺以平坦化凸块的表面; 在经过压印加工的凸块上涂覆焊料; 并且通过熔化焊料材料来接合芯片和凸块，其中在芯片的底部上形成电极部分或金属部分。 对于根据本发明的金属基板，其中包括垂直绝缘层，由于芯片的电极部分和基板的电极部分必须电连接，金属基板被接合到芯片的电极部分 使用另外形成在金属基板上的凸块，使得芯片中产生的热量可以快速转移到基板，并且可以降低芯片的结温，从而提高光效率。 此外，通过使用焊料材料密封芯片的接合部分，可以防止由于焊料材料之间的热膨胀系数的差异导致的破裂。 此外，由于通过阻挡与外部的接触来防止接合部的氧化，所以可以进行芯片封装处理，而不需要在安装芯片的内部空间中填充惰性气体的附加处理。

    Optical Device Array Substrate Having a Heat Dissipating Structure Integrated with a Substrate, and Method for Manufacturing Same
    18.
    发明申请
    Optical Device Array Substrate Having a Heat Dissipating Structure Integrated with a Substrate, and Method for Manufacturing Same 审中-公开
    具有与基板一体化的散热结构的光学器件阵列基板及其制造方法相同

    公开(公告)号：US20140225135A1

    公开(公告)日：2014-08-14

    申请号：US14343674

    申请日：2012-07-26

    Applicant: Point Engineering Co., LTD

    Inventor： Bum Mo Ahn ,  Ki Myung Nam ,  Young Chul Jun

    IPC: H01L33/64

    CPC classification number: H01L33/648 ,  H01L23/3677 ,  H01L23/4006 ,  H01L23/4093 ,  H01L33/642 ,  H01L2224/73265 ,  H01L2933/0075

    Abstract: The present invention relates to an optical device array substrate having a built-in heat dissipating structure, and to a method for manufacturing same, wherein the optical device array substrate itself is used as a heat sink and a coupling hole is formed at the bottom of the substrate to have a heat dissipating rod coupled thereto. The optical device array substrate having a built-in heat dissipating structure of the present invention consists essentially of: an optical device array substrate having a plurality of optical devices arranged on the top surface thereof and a plurality of coupling holes formed in the bottom surface thereof; and rod-shaped heat dissipating rods that have coupling projections formed on upper ends thereof, and are coupled to each of the coupling holes. In the above-described structure, the coupling holes are threaded, and the coupling projections are also threaded so as to be screw-coupled to the coupling holes. The coupling holes are formed having a downwardly narrowing taper, and the coupling projections are formed having a downwardly narrowing taper so as to be precisely coupled with the coupling holes even when in a contracted state under sub-freezing temperatures. The surfaces of the heat dissipating rods are characterized in that insulation coating layers are formed thereon and not on the coupling projections. A portion of the insulation coating layers on some of the heat dissipating rods may be removed to function as electrodes.

    Abstract translation: 本发明涉及具有内置散热结构的光学元件阵列基板及其制造方法，其中光学元件阵列基板本身用作散热器，并且在底部形成有耦合孔 所述基板具有耦合到其上的散热杆。 具有本发明的内置散热结构的光学元件阵列基板主要由以下部分组成：具有设置在其顶面上的多个光学元件的光学元件阵列基板和形成在其底面的多个连接孔 ; 杆状散热杆，其上部形成有联接突起，并且联接到每个连接孔。 在上述结构中，联接孔是螺纹连接的，并且联接突起也是螺纹连接的，以便联接到联接孔。 联接孔形成为具有向下变窄的锥形，并且联接突起形成为具有向下变窄的锥形，以便即使在亚冷冻温度下处于收缩状态下也能与联接孔精确耦合。 散热棒的表面的特征在于其上形成有绝缘涂层，而不在耦合突起上。 一些散热棒上的绝缘涂层的一部分可以被去除以用作电极。

    Probe head and probe card having same
    19.
    发明授权
    Probe head and probe card having same 有权

    公开(公告)号：US12222370B2

    公开(公告)日：2025-02-11

    申请号：US17919739

    申请日：2021-04-20

    Applicant: POINT ENGINEERING CO., LTD.

    Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Sung Hyun Byun

    IPC: G01R1/073 ,  G01R1/067

    Abstract: A probe head and a probe card having the same are provided. The probe head includes a plurality of guide plates each having a guide hole, wherein each of the guide plates has a shape in which a plurality of layers are stacked, and each of the guide plates includes: a first guide layer provided at a lowermost side thereof, and having a first guide hole; and a second guide layer provided at an uppermost side thereof, and having a second guide hole, wherein a side wall of the first guide hole and a side wall of the second guide hole are not provided on the same vertical line.

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