公开(公告)号：BR0014899A

公开(公告)日：2002-10-01

申请号：BR0014899

申请日：2000-10-23

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: G06F11/10 ,  G06F7/38 ,  H03M13/41

Abstract: The present invention discloses a system and system of performing an add-compare-select butterfly operation in an implementation of the Viterbi algorithm. The system includes a first memory element for storing a plurality of source state metrics. The first memory element is coupled to a multiplexer which is capable of selecting between a first and second operating path based on even and odd clock cycles. The multiplexer is coupled to an add-compare-select mechanism, which calculates the target state metrics for each of the source state metrics. A second storage element, coupled to the add-compare-select mechanism and the multiplexer, is used to temporarily store the target state metrics while a third storage element stores a predetermined logic bit which corresponds to the lowest value target state metric. The multiplexer therefore selects the first operating path during even clock cycles and supplies the source state metrics from the first memory element to the add-compare-select mechanism to generate target state metrics. During odd clock cycles, the multiplexer selects the second operating path to access the second memory element and use the previously calculated target state metrics as intermediate source state metrics, such that the add-compare-select mechanism generates the target state metrics based on the intermediate source state metrics.

公开(公告)号：BR9915264A

公开(公告)日：2002-05-28

申请号：BR9915264

申请日：1999-11-10

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID ,  AGRAWAL AVNEESH

IPC: G06F9/46 ,  G06F20060101 ,  G06F15/173 ,  H04J3/02 ,  H04J3/16 ,  H04M3/00 ,  H04Q3/545 ,  H04Q11/00 ,  H04Q11/08

Abstract: A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system supports up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resource allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.

公开(公告)号：BR9912705A

公开(公告)日：2002-01-15

申请号：BR9912705

申请日：1999-08-04

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/41 ,  H04L1/00

Abstract: A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. In one embodiment described herein, the decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainback cache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cache, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. In another embodiment, a full chainback cache is not provided. Rather, the chainback block instead includes an L+1 bit RAM, an updown counter and a shift register configured to emulate a chainback cache. In still another embodiment, an L bit shift register is employed instead of the combination of the L+1 bit RAM and updown counter. In the various embodiments, the chainback block may be configured to perform only one chainback read in each process cycle or may be configured to perform m chainback reads in each process cycle. In still other embodiments, the chainback block is configured to perform chainback operations based on a through b reads where the cache is accessed for each read after a reads have been done until b reads have been performed or a match is obtained. In still further embodiments, the chainback block is configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

公开(公告)号：AU1619300A

公开(公告)日：2000-05-29

申请号：AU1619300

申请日：1999-11-10

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID ,  AGRAWAL AVNEESH

IPC: G06F9/46 ,  G06F20060101 ,  G06F15/173 ,  H04J3/02 ,  H04J3/16 ,  H04M3/00 ,  H04Q3/545 ,  H04Q11/00 ,  H04Q11/08

Abstract: A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system supports up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resource allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.

公开(公告)号：CA2339257A1

公开(公告)日：2000-02-17

申请号：CA2339257

申请日：1999-08-04

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/41 ,  H04L1/00

Abstract: A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. In one embodiment described herein, the decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainback cache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cach e, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. In another embodiment, a full chainback cache is not provided. Rather, the chainback block instead includes an L+1 bit RAM, an updown counter and a shi ft register configured to emulate a chainback cache. In still another embodimen t, an L bit shift register is employed instead of the combination of the L+1 bi t RAM and updown counter. In the various embodiments, the chainback block may be configured to perform only one chainback read in each process cycle or may b e configured to perform m chainback reads in each process cycle. In still othe r embodiments, the chainback block is configured to perform chainback operatio nsbased on a through b reads where the cache is accessed for each read after a reads have been done until b reads have been performed or a match is obtaine d. In still further embodiments, the chainback block is configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

公开(公告)号：HK1040791A1

公开(公告)日：2002-06-21

申请号：HK02102432

申请日：2002-04-02

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID ,  AGRAWAL AVNEESH

IPC: G06F9/46 ,  G06F20060101 ,  G06F15/173 ,  H04J3/02 ,  H04J3/16 ,  H04M3/00 ,  H04Q3/545 ,  H04Q11/00 ,  H04Q11/08 ,  G06F

Abstract: A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system supports up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resource allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.

公开(公告)号：ZA200100914B

公开(公告)日：2002-05-02

申请号：ZA200100914

申请日：2001-02-01

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: H03M13/00 ,  H03M13/41 ,  G06F11/10 ,  H04L1/00 ,  H03M ,  H04L

Abstract: A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. In one embodiment described herein, the decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainback cache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cache, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. In another embodiment, a full chainback cache is not provided. Rather, the chainback block instead includes an L+1 bit RAM, an updown counter and a shift register configured to emulate a chainback cache. In still another embodiment, an L bit shift register is employed instead of the combination of the L+1 bit RAM and updown counter. In the various embodiments, the chainback block may be configured to perform only one chainback read in each process cycle or may be configured to perform m chainback reads in each process cycle. In still other embodiments, the chainback block is configured to perform chainback operations based on a through b reads where the cache is accessed for each read after a reads have been done until b reads have been performed or a match is obtained. In still further embodiments, the chainback block is configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

公开(公告)号：BR9915032A

公开(公告)日：2002-01-02

申请号：BR9915032

申请日：1999-11-05

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: H04J3/00 ,  H03M20060101 ,  H03M13/27 ,  H04B20060101 ,  H04B7/26 ,  H04L12/54

Abstract: A voice and data communication system and method for receiving symbols for a plurality of channels into chunks included within buffers, each chunk holding symbols for only a corresponding one of the plurality of channels. As complete frames are received and decoded, the chunks holding the symbols, that are decoded, are freed up to be used for reception of newly arriving symbols included in newly arriving frames.

公开(公告)号：ID29084A

公开(公告)日：2001-07-26

申请号：ID20011250

申请日：1999-11-10

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID ,  AGRAWAL AVNEESH

IPC: G06F9/46 ,  G06F20060101 ,  G06F15/173 ,  H04J3/02 ,  H04J3/16 ,  H04M3/00 ,  H04Q3/545 ,  H04Q11/00 ,  H04Q11/08

Abstract: A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system supports up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resource allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.

公开(公告)号：AU2021900A

公开(公告)日：2000-05-22

申请号：AU2021900

申请日：1999-11-05

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: H04J3/00 ,  H03M20060101 ,  H03M13/27 ,  H04B20060101 ,  H04B7/26 ,  H04L12/54

Abstract: A voice and data communication system and method for receiving symbols for a plurality of channels into chunks included within buffers, each chunk holding symbols for only a corresponding one of the plurality of channels. As complete frames are received and decoded, the chunks holding the symbols, that are decoded, are freed up to be used for reception of newly arriving symbols included in newly arriving frames.