公开(公告)号：JP2011010311A

公开(公告)日：2011-01-13

申请号：JP2010156837

申请日：2010-07-09

Applicant: Qualcomm Inc ,  クゥアルコム・インコーポレイテッドQualcomm Incorporated

Inventor： HANSQUINE DAVID

IPC: H03M13/27 ,  H04J3/00 ,  H03M20060101 ,  H04B20060101 ,  H04B7/26 ,  H04L12/54

CPC classification number: H03M13/2782 ,  H03M13/2785

Abstract: PROBLEM TO BE SOLVED: To allow a signal for a plurality of channels among a voice and data communication system and a chunk contained in a buffer to be received.SOLUTION: In a method for reducing memory requirement, each chunk holds a symbol for only a corresponding channel of a plurality of channels. When all frames are received and decoded, a chunk which holds a decoded symbol distributes a memory that holds the received symbol in such a way that a vacant capacity, which is used to receive a newly arriving symbol contained in a newly arriving frame, is provided.

Abstract translation: 要解决的问题：允许语音和数据通信系统中的多个信道的信号和包含在缓冲器中的块被接收。解决方案：在一种用于减少存储器需求的方法中，每个块仅保存一个符号 多个信道的相应信道。 当所有帧被接收和解码时，保存解码符号的块分配保存接收到的符号的存储器，使得提供用于接收新到达帧中包含的新到达符号的空闲容量 。

公开(公告)号：AU763225B2

公开(公告)日：2003-07-17

申请号：AU5335799

申请日：1999-08-04

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/41 ,  H04L1/00

Abstract: A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. In one embodiment described herein, the decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainback cache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cache, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. In another embodiment, a full chainback cache is not provided. Rather, the chainback block instead includes an L+1 bit RAM, an updown counter and a shift register configured to emulate a chainback cache. In still another embodiment, an L bit shift register is employed instead of the combination of the L+1 bit RAM and updown counter. In the various embodiments, the chainback block may be configured to perform only one chainback read in each process cycle or may be configured to perform m chainback reads in each process cycle. In still other embodiments, the chainback block is configured to perform chainback operations based on a through b reads where the cache is accessed for each read after a reads have been done until b reads have been performed or a match is obtained. In still further embodiments, the chainback block is configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

公开(公告)号：AU1228501A

公开(公告)日：2001-04-30

申请号：AU1228501

申请日：2000-10-23

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: G06F11/10 ,  G06F7/38 ,  H03M13/41

Abstract: The present invention discloses a system and system of performing an add-compare-select butterfly operation in an implementation of the Viterbi algorithm. The system includes a first memory element for storing a plurality of source state metrics. The first memory element is coupled to a multiplexer which is capable of selecting between a first and second operating path based on even and odd clock cycles. The multiplexer is coupled to an add-compare-select mechanism, which calculates the target state metrics for each of the source state metrics. A second storage element, coupled to the add-compare-select mechanism and the multiplexer, is used to temporarily store the target state metrics while a third storage element stores a predetermined logic bit which corresponds to the lowest value target state metric. The multiplexer therefore selects the first operating path during even clock cycles and supplies the source state metrics from the first memory element to the add-compare-select mechanism to generate target state metrics. During odd clock cycles, the multiplexer selects the second operating path to access the second memory element and use the previously calculated target state metrics as intermediate source state metrics, such that the add-compare-select mechanism generates the target state metrics based on the intermediate source state metrics.

公开(公告)号：ZA9807927B

公开(公告)日：1999-03-01

申请号：ZA9807927

申请日：1998-08-31

Applicant: QUALCOMM INC

Inventor： BUTLER BRIAN K ,  BAYLEY GWAIN ,  HANSQUINE DAVID ,  TIEDEMANN EDWARD G JR

IPC: H03M13/41 ,  H04L1/00 ,  H03K ,  G06F ,  G09C ,  H04B ,  H04L

CPC classification number: H04L1/0071 ,  H03M13/3961 ,  H03M13/3988 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6325 ,  H03M13/6508 ,  H03M13/6583 ,  H04L1/0054

公开(公告)号：NZ509695A

公开(公告)日：2002-08-28

申请号：NZ50969599

申请日：1999-08-04

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: H03M13/00 ,  H03M13/41 ,  G06F11/10 ,  H04L1/00

Abstract: A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. The decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainback cache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cache, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. A full chainback cache need not provided. Rather, the chainback block instead includes an L+1 bit RAM, an updown counter and a shift register configured to emulate a chainback cache or an L bit shift register is employed instead of the combination of the L+1 bit RAM and updown counter. The chainback block may be configured to perform only one chainback read or several reads in each process cycle. The chainback block may be configured to perform chainback operations based on (a) through (b) reads where the cache is accessed for each read after (a) reads have been done until (b) reads have been performed or a match is obtained. The chainback block may be configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

公开(公告)号：CA2387766A1

公开(公告)日：2001-04-26

申请号：CA2387766

申请日：2000-10-23

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: G06F11/10 ,  G06F7/38 ,  H03M13/41

Abstract: System performing an ad-compare-select (ACS) butterfly operation in an implementation of the Viterbi algorithm. The system includes a first memory element (145) for storing a plurality of source state metrics; a multiplexer (670) which is capable of selecting between a first and second operating pat h based on even and odd clock cycles. ACS mechanism (600), which calculates th e target state metrics for each of the source state metrics. A second memory coupled to the ACS mechanism and the multiplexer, is used to temporarily sto re the target metrics. The multiplexer therefore selects the first operating pa th during even clock cycles and supplies the source state metrics from the firs t memory to the ACS mechanism to generate target state metrics. During odd clo ck cycles, the multiplexer selects the second operating path to access the seco nd memory and use the previously calculated target state metrics as intermediat e source state metrics.

公开(公告)号：CA2350572A1

公开(公告)日：2000-05-18

申请号：CA2350572

申请日：1999-11-10

Applicant: QUALCOMM INC

Inventor： AGRAWAL AVNEESH ,  HANSQUINE DAVID

IPC: G06F9/46 ,  G06F20060101 ,  G06F15/173 ,  H04J3/02 ,  H04J3/16 ,  H04M3/00 ,  H04Q3/545 ,  H04Q11/00 ,  H04Q11/08

Abstract: A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system suppor ts up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resour ce allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.

公开(公告)号：AU5335799A

公开(公告)日：2000-02-28

申请号：AU5335799

申请日：1999-08-04

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/41 ,  H04L1/00

Abstract: A serial Viterbi decoder having a chainback cache is provided for use in a mobile telephone. In one embodiment described herein, the decoder includes a branch error metric block, an add-compare-select unit, and a chainback block including a chainback RAM, a full chainback cache and chainback controller circuitry. The chainback cache caches decision bits from previous process cycles such that full chainback operations need not always be performed. The chainback cache is configured to cache on all reads. With the chainback cache, significant savings in power consumption and processing time may be achieved with only a relatively modest increase in the amount of circuitry required. In another embodiment, a full chainback cache is not provided. Rather, the chainback block instead includes an L+1 bit RAM, an updown counter and a shift register configured to emulate a chainback cache. In still another embodiment, an L bit shift register is employed instead of the combination of the L+1 bit RAM and updown counter. In the various embodiments, the chainback block may be configured to perform only one chainback read in each process cycle or may be configured to perform m chainback reads in each process cycle. In still other embodiments, the chainback block is configured to perform chainback operations based on a through b reads where the cache is accessed for each read after a reads have been done until b reads have been performed or a match is obtained. In still further embodiments, the chainback block is configured to perform chainback operations over multiple process cycles rather than only a single process cycle.

公开(公告)号：AU759528B2

公开(公告)日：2003-04-17

申请号：AU2021900

申请日：1999-11-05

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID

IPC: H04J3/00 ,  H03M20060101 ,  H03M13/27 ,  H04B20060101 ,  H04B7/26 ,  H04L12/54

Abstract: A voice and data communication system and method for receiving symbols for a plurality of channels into chunks included within buffers, each chunk holding symbols for only a corresponding one of the plurality of channels. As complete frames are received and decoded, the chunks holding the symbols, that are decoded, are freed up to be used for reception of newly arriving symbols included in newly arriving frames.

公开(公告)号：AU758699B2

公开(公告)日：2003-03-27

申请号：AU1619300

申请日：1999-11-10

Applicant: QUALCOMM INC

Inventor： HANSQUINE DAVID ,  AGRAWAL AVNEESH

IPC: G06F9/46 ,  G06F20060101 ,  G06F15/173 ,  H04J3/02 ,  H04J3/16 ,  H04M3/00 ,  H04Q3/545 ,  H04Q11/00 ,  H04Q11/08

Abstract: A resource allocator for allocating at least two different types of hardware resources for users within a communication system, wherein the system supports up to a first predetermined number of users of one particular type and a second predetermined number of users of a second particular type. The resource allocator provides a mapping of resources, either from fixed resources to shared resources or from shared resources to fixed resources, which is both cost effective and transparent to software.