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    POWER-EFFICIENT MULTI-ANTENNA WIRELESS DEVICE
    11.
    发明专利
    POWER-EFFICIENT MULTI-ANTENNA WIRELESS DEVICE 未知

    公开(公告)号：CA2566329C

    公开(公告)日：2015-05-19

    申请号：CA2566329

    申请日：2005-04-29

    Applicant: QUALCOMM INC

    Inventor： WALTON JAY RODNEY ,  ANTONIO FRANKLIN P ,  WALLACE MARK S ,  NARAYAN SRIRAM

    IPC: H04B1/16 ,  H04J99/00 ,  H04B7/06 ,  H04B7/08

    Abstract: A power-efficient wireless device is equipped with multiple (N) antennas. Each antenna is associated with a transmitter unit and a receiver unit. The wireless device also has processing units used to perform various digital processing tasks. The transmitter units, receiver units, and processing units may be selectively enabled or disabled. In an idle state, the wireless device may enable only a subset (e.g., one) of the N receiver units and one or few processing units for signal detection and acquisition. For active communication, the wireless device may enable Ntx transmitter units for data transmission and/or Nrx receiver units for data reception, where 1

    MEMORY MANAGEMENT FOR HIGH SPEED MEDIA ACCESS CONTROL
    14.
    发明专利
    MEMORY MANAGEMENT FOR HIGH SPEED MEDIA ACCESS CONTROL 未知

    公开(公告)号：CA2644139A1

    公开(公告)日：2007-11-10

    申请号：CA2644139

    申请日：2007-03-30

    Applicant: QUALCOMM INC

    Inventor： DRAVIDA SUBRAHMANYAM ,  NARAYAN SRIRAM

    IPC: H04L12/56 ,  H04L12/28

    Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer.; In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.

    MEMORY MANAGEMENT FOR HIGH SPEED MEDIA ACCESS CONTROL
    16.
    发明申请
    MEMORY MANAGEMENT FOR HIGH SPEED MEDIA ACCESS CONTROL 审中-公开
    高速媒体访问控制的内存管理

    公开(公告)号：WO2007115199A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2007065678

    申请日：2007-03-30

    Applicant: QUALCOMM INC ,  DRAVIDA SUBRAHMANYAM ,  NARAYAN SRIRAM

    Inventor： DRAVIDA SUBRAHMANYAM ,  NARAYAN SRIRAM

    IPC: H04L12/56 ,  H04L12/28

    CPC classification number: H04L49/901 ,  H04L47/14 ,  H04L47/621 ,  H04L49/90 ,  H04L49/9021 ,  H04L49/9073 ,  H04W36/02 ,  H04W36/28 ,  H04W76/04 ,  H04W88/02 ,  H04W88/08

    Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer. In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.

    Abstract translation: 本文公开的方面解决了本领域对用于高速媒体访问控制的存储器管理的需要。 分组缓冲器可以存储具有第一数据结构的分组，包括分组长度，序列号和指向第二数据结构的指针。 分组数据可以存储在一个或多个第二数据结构的链接列表中。 发送和接收队列可以使用第一数据结构的链表或数组来形成。 用于存储第一和第二数据结构的存储器位置可以保存在指示相应数据结构类型的空闲位置的列表中。 公开了一种灵活的存储器架构，其中可以选择两种配置。 在第一配置中，第一存储器包括用于多个流的每流参数，并且第二存储器包括分组缓冲器。 在第二配置中，第一存储器包括在第二存储器中的每流参数的每流指针。 数据包缓冲区位于第三个存储器中。 还提出了各种其他方面。

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