-
公开(公告)号：JP2011103672A
公开(公告)日：2011-05-26
申请号：JP2010278357
申请日：2010-12-14
Applicant: Qualcomm Inc , クゥアルコム・インコーポレイテッドQualcomm Incorporated
Inventor： WALTON JAY RODNEY , ANTONIO FRANKLIN P , WALLACE MARK S , NARAYAN SRIRAM
CPC classification number: H04W52/029 , H04W52/0274 , Y02D70/00
Abstract: PROBLEM TO BE SOLVED: To provide a power-efficient wireless device provided with multiple (N) antennas.
SOLUTION: Each antenna is associated with a transmitter unit and a receiver unit. The wireless device also has processing units used to perform various digital processing tasks. The transmitter units, the receiver units and the processing units may be selectively enabled or disabled. In an idle state, the wireless device may enable only a subset (e.g., one) of the N receiver units and one or few processing units for signal detection and acquisition. For active communication, the wireless device may enable N
tx transmitter units for data transmission and/or N
rx receiver units for data reception, where 1≤N
tx ≤N and 1≤N
rx ≤N.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 要解决的问题：提供具有多（N）个天线的功率高效无线设备。
解决方案：每个天线与发射机单元和接收机单元相关联。 无线设备还具有用于执行各种数字处理任务的处理单元。 可以选择性地启用或禁用发射机单元，接收机单元和处理单元。 在空闲状态下，无线设备可以仅使得N个接收机单元中的子集（例如，一个）和用于信号检测和获取的一个或几个处理单元。 对于主动通信，无线设备可以使N
tx 个发送单元用于数据发送和/或N rx 个接收单元进行数据接收，其中1≤N / SB>≤N和1≤N rx ≤N。 版权所有（C）2011，JPO＆INPIT -
公开(公告)号：CA2566329A1
公开(公告)日：2005-12-01
申请号：CA2566329
申请日：2005-04-29
Applicant: QUALCOMM INC
Inventor： WALLACE MARK S , NARAYAN SRIRAM , ANTONIO FRANKLIN P , WALTON JAY RODNEY
Abstract: A multi-antenna wireless device (100) comprising a plurality of (N) transmitter units (120) operatively coupled to a plurality of antennas (122), one transmitter unit (120) for each set of at least one antenna from among the plurality of antennas (122), each transmitter unit (120) operable to process a respective input signal and provide an output signal; a plurality of processing units (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232), each processing unit operable to perform designated processing for data transmission; and a controller (140, 230) that selectively and individually enables or disables at least one of the N transmitter units (120) and at least one of the plurality of processing units (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232).
-
公开(公告)号：AT486410T
公开(公告)日：2010-11-15
申请号：AT09169494
申请日：2005-04-29
Applicant: QUALCOMM INC
Inventor： WALTON JAY , WALLACE MARK , ANTONIO FRANKLIN P , NARAYAN SRIRAM
Abstract: A multi-antenna wireless device (100) comprising a plurality of (N) transmitter units (120) operatively coupled to a plurality of antennas (122), one transmitter unit (120) for each set of at least one antenna from among the plurality of antennas (122), each transmitter unit (120) operable to process a respective input signal and provide an output signal; a plurality of processing units (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232), each processing unit operable to perform designated processing for data transmission; and a controller (140, 230) that selectively and individually enables or disables at least one of the N transmitter units (120) and at least one of the plurality of processing units (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232).
-
公开(公告)号：DE602005017266D1
公开(公告)日：2009-12-03
申请号：DE602005017266
申请日：2005-04-29
Applicant: QUALCOMM INC
Inventor： WALTON JAY RODNEY , ANTONIO FRANKLIN P , WALLACE MARK S , NARAYAN SRIRAM
Abstract: A multi-antenna wireless device (100) comprising a plurality of (N) transmitter units (120) operatively coupled to a plurality of antennas (122), one transmitter unit (120) for each set of at least one antenna from among the plurality of antennas (122), each transmitter unit (120) operable to process a respective input signal and provide an output signal; a plurality of processing units (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232), each processing unit operable to perform designated processing for data transmission; and a controller (140, 230) that selectively and individually enables or disables at least one of the N transmitter units (120) and at least one of the plurality of processing units (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232).
-
公开(公告)号：BRPI0722378A2
公开(公告)日：2012-05-22
申请号：BRPI0722378
申请日：2007-03-30
Applicant: QUALCOMM INC
Inventor： DRAVIDA SUBRAHMANYAM , NARAYAN SRIRAM
Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer.; In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.
-
Patent Agency Ranking
公开(公告)号：BRPI0709704A2
公开(公告)日：2011-05-10
申请号：BRPI0709704
申请日：2007-03-30
Applicant: QUALCOMM INC
Inventor： DRAVIDA SUBRAHMANYAM , NARAYAN SRIRAM
Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer.; In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.
-
公开(公告)号：ES2335675T3
公开(公告)日：2010-03-31
申请号：ES05744347
申请日：2005-04-29
Applicant: QUALCOMM INC
Inventor： WALTON JAY RODNEY , ANTONIO FRANKLIN P , WALLACE MARK S , NARAYAN SRIRAM
Abstract: Dispositivo inalámbrico de múltiples antenas (100) que comprende: una pluralidad de (N) unidades transmisoras (120) operativamente acopladas a una pluralidad de antenas (122), una unidad transmisora (120) para cada conjunto de por lo menos una antena de entre la pluralidad de antenas (122), siendo cada unidad transmisora (120) operable para procesar una respectiva señal de entrada y proporcionar una señal de salida; una pluralidad de unidades de procesamiento (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232), siendo cada unidad de procesamiento operable para llevar a cabo un procesamiento indicado para la transmisión de datos; medios (140, 230) para selectivamente e individualmente habilitar o deshabilitar por lo menos una de las N unidades transmisoras (120); y medios (140, 230) para selectivamente e individualmente habilitar o deshabilitar por lo menos una de entre la pluralidad de unidades de procesamiento (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232).
-
公开(公告)号：AT543304T
公开(公告)日：2012-02-15
申请号：AT07759865
申请日：2007-03-30
Applicant: QUALCOMM INC
Inventor： DRAVIDA SUBRAHMANYAM , NARAYAN SRIRAM
IPC: H04L12/56
Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer.; In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.
-
公开(公告)号：SG163590A1
公开(公告)日：2010-08-30
申请号：SG2010049518
申请日：2007-03-30
Applicant: QUALCOMM INC
Inventor： DRAVIDA SUBRAHMANYAM , NARAYAN SRIRAM
Abstract: Aspects disclosed herein address the need in the art for memory management for high speed media access control. A packet buffer may store packets with a first data structure, comprising the packet length, sequence number, and a pointer to a second data structure. Packet data may be stored in a linked list of one or more second data structures. Transmit and receive queues may be formed using linked lists or arrays of the first data structures. Memory locations for storing first and second data structures may be kept in lists indicating free locations for the respective data structure types. A flexible memory architecture is disclosed in which two configurations may be selected. In a first configuration, a first memory comprises per-flow parameters for multiple flows, and a second memory comprises a packet buffer. In a second configuration, the first memory comprises per-flow pointers to per-flow parameters in the second memory. The packet buffer resides in a third memory. Various other aspects are also presented.
-
公开(公告)号：AT446615T
公开(公告)日：2009-11-15
申请号：AT05744347
申请日：2005-04-29
Applicant: QUALCOMM INC
Inventor： WALTON JAY , ANTONIO FRANKLIN , WALLACE MARK , NARAYAN SRIRAM
Abstract: A multi-antenna wireless device (100) comprising a plurality of (N) transmitter units (120) operatively coupled to a plurality of antennas (122), one transmitter unit (120) for each set of at least one antenna from among the plurality of antennas (122), each transmitter unit (120) operable to process a respective input signal and provide an output signal; a plurality of processing units (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232), each processing unit operable to perform designated processing for data transmission; and a controller (140, 230) that selectively and individually enables or disables at least one of the N transmitter units (120) and at least one of the plurality of processing units (114, 116, 118, 132, 134, 136, 210, 212, 214, 216, 218, 220, 232).
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.021 seconds)
