公开(公告)号：WO2014113288A1

公开(公告)日：2014-07-24

申请号：PCT/US2014/011051

申请日：2014-01-10

Applicant: QUALCOMM INCORPORATED

Inventor： SASSONE, Peter G. ,  VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian

IPC: G06F9/38

CPC classification number: G06F12/0864 ,  G06F9/3455 ,  G06F9/3832 ,  G06F2212/6082

Abstract: In a particular embodiment, a method includes identifying one or more way prediction characteristics of an instruction. The method also includes selectively reading, based on identification of the one or more way prediction characteristics, a table to identify an entry of the table associated with the instruction that identifies a way of a data cache. The method further includes making a prediction whether a next access of the data cache based on the instruction will access the way.

Abstract translation: 在特定实施例中，一种方法包括识别指令的一种或多种方式预测特征。 该方法还包括基于一个或多个方式预测特征的识别来选择性地读取用于标识与标识数据高速缓存的方式相关联的表的条目的表。 该方法还包括基于该指令来预测数据高速缓存的下一次访问是否将访问的方式。

公开(公告)号：WO2014100632A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/077020

申请日：2013-12-20

Applicant: QUALCOMM INCORPORATED

Inventor： SASSONE, Peter G. ,  VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3832 ,  G06F12/0864 ,  G06F2212/6082 ,  Y02D10/13

Abstract: In a particular embodiment, an apparatus includes control logic configured to selectively set bits of a multi-bit way prediction mask based on a prediction mask value. The control logic is associated with an instruction cache including a data array. A subset of line drivers of the data array is enabled responsive to the multi-bit way prediction mask. The subset of line drivers includes multiple line drivers.

Abstract translation: 在特定实施例中，一种装置包括配置成基于预测掩模值有选择地设置多位方式预测掩码的比特的控制逻辑。 控制逻辑与包括数据阵列的指令高速缓存相关联。 数据阵列的线路驱动器的子集响应于多位方式预测掩码而被启用。 线路驱动器的子集包括多个线路驱动器。

公开(公告)号：WO2013181425A1

公开(公告)日：2013-12-05

申请号：PCT/US2013/043417

申请日：2013-05-30

Applicant: QUALCOMM INCORPORATED

Inventor： ZENG, Mao ,  PLONDKE, Erich, James ,  CODRESCU, Lucian

IPC: G06K9/46

CPC classification number: G06K9/4638

Abstract: A method of determining whether a particular pixel of an image is a feature candidate includes receiving data corresponding to a subset of a plurality of pixels surrounding the particular pixel. Each of the plurality of pixels may be from the image. The method further includes excluding the particular pixel from consideration as a feature candidate based on a comparison of values of the data to a comparison value. The comparison value may be based on an attribute value of the particular pixel and a threshold attribute value.

Abstract translation: 确定图像的特定像素是否是特征候选的方法包括接收对应于围绕特定像素的多个像素的子集的数据。 多个像素中的每一个可以来自图像。 该方法还包括基于将数据的值与比较值的比较来排除特定像素作为特征候选。 比较值可以基于特定像素的属性值和阈值属性值。

公开(公告)号：WO2013106583A1

公开(公告)日：2013-07-18

申请号：PCT/US2013/021050

申请日：2013-01-10

Applicant: QUALCOMM Incorporated

Inventor： PLONDKE, Erich, James ,  INGLE, Ajay, Anant ,  CODRESCU, Lucian

IPC: G06F12/10 ,  G06F9/30 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0888 ,  G06F12/1027

Abstract: Systems and methods for performing non-allocating memory access instructions with physical address. A system includes a processor, one or more levels of caches, a memory, a translation look-aside buffer (TLB), and a memory access instruction specifying a memory access by the processor and an associated physical address. Execution logic is configured to bypass the TLB for the memory access instruction and perform the memory access with the physical address, while avoiding allocation of one or more intermediate levels of caches where a miss may be encountered.

Abstract translation: 用于执行具有物理地址的非分配存储器访问指令的系统和方法。 系统包括处理器，一个或多个级别的高速缓存，存储器，翻译后备缓冲器（TLB）以及指定处理器的存储器访问和相关联的物理地址的存储器访问指令。 执行逻辑被配置为绕过用于存储器访问指令的TLB并且使用物理地址执行存储器访问，同时避免分配可能遇到未命中的一个或多个中间级别的高速缓存。

公开(公告)号：WO2013086060A1

公开(公告)日：2013-06-13

申请号：PCT/US2012/068050

申请日：2012-12-05

Applicant: QUALCOMM INCORPORATED

Inventor： INGLE, Ajay Anant ,  CODRESCU, Lucian

IPC: G06F12/08

CPC classification number: G06F12/0855 ,  G06F2212/1028 ,  Y02D10/13

Abstract: An apparatus includes a cache memory that includes a state array configured to store state information. The state information includes a state that indicates updated corresponding to a particular address of the cache memory is not stored in the cache memory but is available from at least one of multiple sources external to the cache memory, where at least one of the multiple sources is a store buffer.

Abstract translation: 一种装置包括高速缓冲存储器，其包括配置为存储状态信息的状态阵列。 状态信息包括指示与高速缓冲存储器的特定地址对应的更新的状态未被存储在高速缓冲存储器中，但是可以从高速缓冲存储器外部的多个源中的至少一个获得，其中多个源中的至少一个是 一个商店缓冲区。

公开(公告)号：WO2013049765A1

公开(公告)日：2013-04-04

申请号：PCT/US2012/058181

申请日：2012-09-30

Applicant: QUALCOMM INCORPORATED ,  ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant

Inventor： ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich James ,  INGLE, Ajay Anant

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30032 ,  G06F9/30043

Abstract: An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.

Abstract translation: 指令识别寄存器和存储器位置。 在由处理器执行指令时，从存储器位置加载一个物品，并执行移位和插入操作以移位寄存器中的数据并将该项目插入到寄存器中。

公开(公告)号：WO2013044260A2

公开(公告)日：2013-03-28

申请号：PCT/US2012/056960

申请日：2012-09-24

Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich J. ,  CODRESCU, Lucian ,  ZENG, Mao ,  BALASUBRAMANIAN, Swaminathan ,  HOYLE, David J.

Inventor： PLONDKE, Erich J. ,  CODRESCU, Lucian ,  ZENG, Mao ,  BALASUBRAMANIAN, Swaminathan ,  HOYLE, David J.

IPC: G06F7/02

CPC classification number: G06F9/30021 ,  G06F7/544 ,  G06F9/30036 ,  G06F17/18

Abstract: An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.

Abstract translation: 公开了一种确定极值的装置，系统和方法。 参考位置标识符和参考极值被耦合。 确定输入数据集的输入极值，并确定输入极值的相应位置标识符。 基于比较，将输入极值与参考极值进行比较，以确定输出极值和输出位置标识符。

公开(公告)号：WO2013016737A1

公开(公告)日：2013-01-31

申请号：PCT/US2012/048904

申请日：2012-07-30

Applicant: QUALCOMM INCORPORATED ,  LARIN, Sergei ,  CODRESCU, Lucian ,  DAS GUPTA, Anshuman

Inventor： LARIN, Sergei ,  CODRESCU, Lucian ,  DAS GUPTA, Anshuman

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30178 ,  G06F9/30156 ,  G06F9/3017 ,  G06F9/3853

Abstract: A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Yindex together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.

Abstract translation: 一种压缩程序指令序列的方法是通过检查程序指令流来识别符合参数的两个或多个指令的序列开始的。 所识别的两个或多个指令的序列被选择的布局指令类型替换，然后被压缩。 解压缩方法将X索引和Yindex一起访问为压缩值。 将压缩值解压缩为选定类型的布局指令，该指令被解码并用两个或更多个指令的序列代替。 用于解压缩的装置包括被配置为存储压缩指令的存储子系统，其中压缩指令包括X索引和Y索引。 解压缩器被配置为将从存储子系统访问的X索引和Y索引转换为选择类型的布局指令，该指令被解码并用两个或更多个指令的序列替代。

公开(公告)号：WO2012064677A1

公开(公告)日：2012-05-18

申请号：PCT/US2011/059658

申请日：2011-11-07

Applicant: QUALCOMM INCORPORATED ,  VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian ,  SHANNON, Stephen R. ,  WANG, Lin ,  JONES, Phillip M. ,  PALAL, Daisy T. ,  TU, Jiajin

Inventor： VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian ,  SHANNON, Stephen R. ,  WANG, Lin ,  JONES, Phillip M. ,  PALAL, Daisy T. ,  TU, Jiajin

IPC: G06F9/38

CPC classification number: G06F9/3844

Abstract: Each branch instruction having branch prediction support has branch prediction bits in architecture specified bit positions in the branch instruction. An instruction cache supports modifying the branch instructions with updated branch prediction bits that are dynamically determined when the branch instruction executes.

Abstract translation: 具有分支预测支持的每个分支指令在分支指令中的架构指定的位位置具有分支预测位。 指令高速缓存支持使用在分支指令执行时动态确定的更新的分支预测位修改分支指令。

公开(公告)号：WO2010107774A2

公开(公告)日：2010-09-23

申请号：PCT/US2010/027453

申请日：2010-03-16

Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich, James ,  CODRESCU, Lucian

Inventor： PLONDKE, Erich, James ,  CODRESCU, Lucian

IPC: G06F9/06 ,  G06F9/30 ,  G06F13/14 ,  G06F9/44

CPC classification number: G06F9/3851 ,  G06F9/4812 ,  G06F9/4881

Abstract: In a particular embodiment, a method is disclosed that includes receiving an interrupt at a first thread, the first thread including a lowest priority thread of a plurality of executing threads at a processor at a first time. The method also includes identifying a second thread, the second thread including a lowest priority thread of a plurality of executing threads at a processor at a second time. The method further includes directing a subsequent interrupt to the second thread.

Abstract translation: 在特定实施例中，公开了一种包括在第一线程处接收中断的方法，所述第一线程在第一时间包括处理器处的多个执行线程的最低优先级线程。 所述方法还包括识别第二线程，所述第二线程在第二时间包括处理器处的多个执行线程的最低优先级线程。 该方法还包括将后续中断引导到第二线程。