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    BIMODAL COMPARE PREDICTOR ENCODED IN EACH COMPARE INSTRUCTION
    2.
    发明申请
    BIMODAL COMPARE PREDICTOR ENCODED IN EACH COMPARE INSTRUCTION 审中-公开
    在每个比较指令中编写的双模比较预测

    公开(公告)号：WO2013158889A1

    公开(公告)日：2013-10-24

    申请号：PCT/US2013/037185

    申请日：2013-04-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： TABONY, Charles Joseph ,  CODRESCU, Lucian ,  VENKUMAHANTI, Suresh K.

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F9/30021 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3832

    Abstract: Systems and methods for branch prediction, including predicting evaluation of a producer instruction (102) such as a compare instruction, by encoding a prediction field (102p) in the producer instruction, and predicting evaluation (107, using 104, 106) of the producer instruction by using the encoded prediction field. A consumer instruction such as a conditional branch instruction predicated on the producer instruction can be speculatively executed based on the predicted evaluation of the producer instruction. The producer instruction is executed in an execution pipeline (112) to determine an actual evaluation (113) of the producer instruction, and if necessary, the prediction field is updated by update logic based on the actual evaluation and the predicted evaluation. The producer instruction can be updated in memory (108) with the updated prediction field.

    Abstract translation: 用于分支预测的系统和方法，包括通过对生成器指令中的预测字段（102p）进行编码以及预测生产者的评估（107,104,106）来预测诸如比较指令的生成器指令（102）的评估 通过使用编码预测字段进行指令。 可以基于生成器指令的预测评估，推测性地执行诸如基于生成器指令的条件分支指令的消费者指令。 在执行管线（112）中执行生成器指令以确定生产者指令的实际评估（113），并且如果需要，基于实际评估和预测评估，通过更新逻辑更新预测字段。 可以利用更新的预测字段在存储器（108）中更新生成器指令。

    SELECTIVE WRITING OF BRANCH TARGET BUFFER
    3.
    发明申请
    SELECTIVE WRITING OF BRANCH TARGET BUFFER 审中-公开
    分支目标缓冲区的选择性写作

    公开(公告)号：WO2013067515A1

    公开(公告)日：2013-05-10

    申请号：PCT/US2012/063581

    申请日：2012-11-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： VENKUMAHANTI, Suresh K. ,  CODRESCU, Lucian ,  MAMIDI, Suman

    IPC: G06F9/38

    CPC classification number: G06F9/3806 ,  G06F9/3844

    Abstract: A method includes executing a branch instruction and determining if a branch is taken. The method further includes evaluating a number of instructions associated with the branch instruction. Upon determining that the branch is taken, the method includes selectively writing an entry into a branch target buffer that corresponds to the taken branch responsive to determining that the number of instructions is less than a threshold.

    Abstract translation: 一种方法包括执行分支指令并确定是否采用分支。 该方法还包括评估与分支指令相关联的多个指令。 在确定分支被采取时，该方法包括响应于确定指令数量小于阈值而选择性地将条目写入对应于所采取的分支的分支目标缓冲器。

    MEMORY WITH METADATA STORED IN A PORTION OF THE MEMORY PAGES
    4.
    发明申请
    MEMORY WITH METADATA STORED IN A PORTION OF THE MEMORY PAGES 审中-公开
    存储在存储器页的存储器中的存储器

    公开(公告)号：WO2012162225A1

    公开(公告)日：2012-11-29

    申请号：PCT/US2012/038794

    申请日：2012-05-21

    Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich, James ,  CODRESCU, Lucian ,  ANDERSON, William, C.

    Inventor： PLONDKE, Erich, James ,  CODRESCU, Lucian ,  ANDERSON, William, C.

    IPC: G06F11/10

    CPC classification number: G06F12/0893 ,  G06F11/1064 ,  G06F12/0646 ,  Y02D10/13

    Abstract: Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.

    Abstract translation: 用于配置基于页面的存储设备而不具有预先存在的专用元数据的系统和方法。 该方法包括从存储设备的页面的元数据部分读取元数据，以及基于元数据确定页面的特性。 存储器件可以被配置为高速缓存。 元数据可以包括地址标签，使得确定特征可以包括确定页面中是否存在所需信息，并且如果确定存在于页面中则读取所需信息。 元数据还可以包括纠错码（ECC），使得确定特性可以包括检测存在于页面中的数据中存在的错误。 元数据还可以包括目录信息，存储器一致性信息或脏/有效/锁定信息。

    THREAD ALLOCATION AND CLOCK CYCLE ADJUSTMENT IN AN INTERLEAVED MULTI-THREADED PROCESSOR
    5.
    发明申请
    THREAD ALLOCATION AND CLOCK CYCLE ADJUSTMENT IN AN INTERLEAVED MULTI-THREADED PROCESSOR 审中-公开
    交叉多线程处理器中的螺纹分配和时钟周期调整

    公开(公告)号：WO2011072083A1

    公开(公告)日：2011-06-16

    申请号：PCT/US2010/059579

    申请日：2010-12-08

    Applicant: QUALCOMM INCORPORATED ,  VENKUMAHANTI, Suresh, K. ,  SAINT-LAURENT, Martin ,  CODRESCU, Lucian ,  MOHAMMAD, Baker, S.

    Inventor： VENKUMAHANTI, Suresh, K. ,  SAINT-LAURENT, Martin ,  CODRESCU, Lucian ,  MOHAMMAD, Baker, S.

    IPC: G06F9/38 ,  G06F9/50

    CPC classification number: G01R1/07378 ,  G01R3/00 ,  G01R31/2846 ,  G01R31/2889 ,  G01R31/2896 ,  G06F9/3851

    Abstract: Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.

    Abstract translation: 公开了用于通过减少多线程处理器中的硬件线程切换来降低功率的方法，装置和计算机可读存储介质。 在特定实施例中，一种方法将软件线程分配给硬件线程。 识别要分配的多个软件线程。 何时软件线程的数量少于多个硬件线程。 当软件线程的数量小于硬件线程数时，至少两个软件线程被分配给非顺序硬件线程。 响应于所分配的非顺序硬件线程调整应用于硬件线程的时钟信号。

    EMBEDDED TRACE MACROCELL FOR ENHANCED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS
    9.
    发明申请
    EMBEDDED TRACE MACROCELL FOR ENHANCED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS 审中-公开
    用于增强型数字信号处理器调试操作的嵌入式宏跟踪器

    公开(公告)号：WO2008061102A2

    公开(公告)日：2008-05-22

    申请号：PCT/US2007/084578

    申请日：2007-11-13

    Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    IPC: G06F11/36

    CPC classification number: G06F11/3656 ,  G06F9/3005

    Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

    Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 该方法和系统通过捕获与软件执行流有关的实时信息来改进软件指令调试操作，并且包括用于在核心处理器内操作核心处理器过程的指令和电路。 非侵入式调试过程在数字信号处理器的调试机制内运行。 实时非侵入式地监控软件执行的预定方面与核心处理过程一起发生并且在处理器上实时发生。 嵌入式跟踪宏小区记录非侵入式监控的软件执行的可选方面并且响应于在非侵入式监控的软件执行的可选方面内出现的事件而产生至少一个断点。 本公开内容响应于至少一个断点来控制非侵入式调试过程的各个方面。

    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS
    10.
    发明申请
    SYSTEMS AND METHODS OF EXECUTING MULTIPLE HYPERVISORS 审中-公开
    多重执行机构的系统与方法

    公开(公告)号：WO2014159405A1

    公开(公告)日：2014-10-02

    申请号：PCT/US2014/023445

    申请日：2014-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： PLONDKE, Erich James ,  CODRESCU, Lucian ,  KOOB, Christopher Edward ,  PATEL, Piyush ,  SARTORIUS, Thomas Andrew

    IPC: G06F9/455 ,  G06F9/50 ,  G06F12/10

    CPC classification number: G06F9/45533 ,  G06F9/5016 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/151 ,  G06F2212/656

    Abstract: An apparatus includes a primary hypervisor that is executable on a first set of processors and a secondary hypervisor that is executable on a second set of processors. The primary hypervisor may define settings of a resource and the secondary hypervisor may use the resource based on the settings defined by the primary hypervisor. For example, the primary hypervisor may program memory address translation mappings for the secondary hypervisor. The primary hypervisor and the secondary hypervisor may include their own schedulers.

    Abstract translation: 一种装置包括可在第一组处理器上执行的主管理程序，以及可在第二组处理器上执行的辅管理程序。 主管理程序可以定义资源的设置，次管理程序可以使用基于主管理程序定义的设置的资源。 例如，主管理程序可以为二级管理程序编程内存地址转换映射。 主管理程序和辅助管理程序可以包括它们自己的调度器。

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