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    PACKAGE-ON-PACKAGE (POP) STRUCTURE
    11.
    发明申请
    PACKAGE-ON-PACKAGE (POP) STRUCTURE 审中-公开
    PACKAGE-ON-PACKAGE（POP）结构

    公开(公告)号：WO2016123115A1

    公开(公告)日：2016-08-04

    申请号：PCT/US2016/014939

    申请日：2016-01-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： WE, Hong Bok ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung

    IPC: H01L25/10 ,  H01L23/498 ,  H01L21/48

    CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157

    Abstract: A method for forming a package-on-package (POP) structure is disclosed. The method includes placing a post on a first integrated circuit (IC) package such that a solder coating disposed on a first surface of the post is between the post and a second surface of the first IC package. The post is placed at a distance from a die along a particular axis of the die. The particular axis is substantially parallel to the second surface. The first IC package includes the die. The method also includes forming a conductive path between a second IC package and the first IC package via the post and a solder bump. The solder bump is disposed between the post and the second IC package.

    Abstract translation: 公开了一种用于形成封装封装（POP）结构的方法。 该方法包括将柱放置在第一集成电路（IC）封装上，使得设置在柱的第一表面上的焊料涂层位于第一IC封装的柱和第二表面之间。 柱沿模具的特定轴线放置在与模具相距一定距离处。 特定轴线基本上平行于第二表面。 第一个IC封装包括裸片。 该方法还包括在第二IC封装和第一IC封装之间经由柱和焊料凸块形成导电路径。 焊料凸块设置在柱和第二IC封装之间。

    EMBEDDED PACKAGE SUBSTRATE CAPACITOR
    13.
    发明申请
    EMBEDDED PACKAGE SUBSTRATE CAPACITOR 审中-公开
    嵌入式封装衬底电容器

    公开(公告)号：WO2015179305A1

    公开(公告)日：2015-11-26

    申请号：PCT/US2015/031394

    申请日：2015-05-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： WE, Hong Bok ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu ,  KIM, Dong Wook

    IPC: H01L23/498 ,  H01L23/50

    CPC classification number: H01L28/40 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/185 ,  H05K3/4602 ,  H01L2924/014

    Abstract: A package substrate is provided that includes a core substrate and a capacitor embedded in the core substrate including a first side. The capacitor includes a first electrode and a second electrode disposed at opposite ends of the capacitor. The package also includes a first power supply metal plate extending laterally in the core substrate. The first power supply metal plate is disposed directly on the first electrode of the capacitor from the first side of the core substrate. A first via extending perpendicular to the first metal plate and connected to the first power supply metal plate from the first side of the core substrate.

    Abstract translation: 提供一种封装基板，其包括芯基板和嵌入在包括第一侧的芯基板中的电容器。 电容器包括设置在电容器的相对端的第一电极和第二电极。 封装还包括在芯基板中横向延伸的第一电源金属板。 第一电源金属板从芯基板的第一侧直接设置在电容器的第一电极上。 第一通孔，其垂直于第一金属板延伸并从芯基板的第一侧连接到第一电源金属板。

    MULTILAYER CERAMIC CAPACITOR INCLUDING AT LEAST ONE SLOT
    14.
    发明申请
    MULTILAYER CERAMIC CAPACITOR INCLUDING AT LEAST ONE SLOT 审中-公开
    多层陶瓷电容器，包括至少一个插槽

    公开(公告)号：WO2015080847A1

    公开(公告)日：2015-06-04

    申请号：PCT/US2014/064290

    申请日：2014-11-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： YUN, Changhan Hobie ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu ,  KIM, Dong Wook

    IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12

    CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12

    Abstract: An apparatus includes a two-terminal MLCC. The two-terminal MLCC includes a conductive layer, where the conductive layer includes at least one slot. The apparatus may also include a second conductive layer that includes at least one slot and an insulating layer that separates the two conductive layers. In one example, a first (e.g., positive) terminal of the two-terminal MLCC is formed by a first set of plates, where each plate in the first set includes at least one slot. A second (e.g., negative) terminal of the two-terminal MLCC is formed by a second set of plates, where each plate in the second set also includes at least one slot. The first set of plates and the second set of plates are interleaved, and each pair of plates is separated by an insulating layer.

    Abstract translation: 一种装置包括两端MLCC。 双端MLCC包括导电层，其中导电层包括至少一个槽。 该装置还可以包括第二导电层，其包括至少一个槽和分离两个导电层的绝缘层。 在一个示例中，双端子MLCC的第一（例如，正）端子由第一组板形成，其中第一组中的每个板包括至少一个槽。 双端子MLCC的第二（例如，负极）端子由第二组板形成，其中第二组中的每个板还包括至少一个槽。 第一组板和第二组板被交错，并且每对板由绝缘层分开。

    INTEGRATED DEVICE COMPRISING COAXIAL INTERCONNECT
    15.
    发明公开
    INTEGRATED DEVICE COMPRISING COAXIAL INTERCONNECT 审中-公开
    包含同轴互连的集成器件

    公开(公告)号：EP3167483A1

    公开(公告)日：2017-05-17

    申请号：EP15741706.4

    申请日：2015-07-09

    Applicant: Qualcomm Incorporated

    Inventor： KIM, Dong Wook ,  SONG, Young Kyu ,  HWANG, Kyu-Pyung ,  WE, Hong Bok

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K3/284 ,  H05K3/46 ,  H05K2203/1316

    Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

    Abstract translation: 一些新颖特征涉及一种集成装置，其包括衬底，耦合到衬底的第一互连以及围绕第一互连的第二互连。 第二互连可以被配置为提供到地的电连接。 在一些实施方式中，第二互连件包括板。 在一些实现中，集成器件还包括介于第一互连和第二互连之间的电介质材料。 在一些实施方式中，集成装置还包括围绕第二互连的模具。 在一些实现中，第一互连被配置为在第一方向上传导功率信号。 在一些实现中，第二互连被配置为在第二方向上传导接地信号。 在一些实现中，第二方向不同于第一方向。 在一些实现中，集成设备可以是封装级封装（PoP）设备。

    ELECTROMAGNETIC INTERFERENCE ENCLOSURE FOR RADIO FREQUENCY MULTI-CHIP INTEGRATED CIRCUIT PACKAGES
    16.
    发明公开
    ELECTROMAGNETIC INTERFERENCE ENCLOSURE FOR RADIO FREQUENCY MULTI-CHIP INTEGRATED CIRCUIT PACKAGES 审中-公开
    电磁干扰射频多芯片集成电路封装HOUSING

    公开(公告)号：EP2973696A1

    公开(公告)日：2016-01-20

    申请号：EP14715158.3

    申请日：2014-03-06

    Applicant: Qualcomm Incorporated

    Inventor： HWANG, Kyu-Pyung ,  SONG, Young Kyu ,  KIM, Dong Wook ,  YUN, Changhan

    IPC: H01L23/552 ,  H01L25/065 ,  H05K9/00 ,  H01L23/66

    Abstract: One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.

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