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    FLEXIBLE FILM ELECTRICAL-TEST SUBSTRATES WITH CONDUCTIVE COUPLING POST(S) FOR INTEGRATED CIRCUIT (IC) BUMP(S) ELECTRICAL TESTING, AND RELATED METHODS AND TESTING APPARATUSES
    4.
    发明申请
    FLEXIBLE FILM ELECTRICAL-TEST SUBSTRATES WITH CONDUCTIVE COUPLING POST(S) FOR INTEGRATED CIRCUIT (IC) BUMP(S) ELECTRICAL TESTING, AND RELATED METHODS AND TESTING APPARATUSES 审中-公开
    用于集成电路（IC）电气测试及其相关方法和测试装置的具有导电耦合功能的柔性薄膜电测试基板

    公开(公告)号：WO2016048626A1

    公开(公告)日：2016-03-31

    申请号：PCT/US2015/048539

    申请日：2015-09-04

    Applicant: QUALCOMM INCORPORATED

    Inventor： SONG, Young Kyu ,  WE, Hong Bok ,  KIM, Dong Wook ,  KIM, Chin-Kwan ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  KANG, Seung, Hyuk

    IPC: G01R1/073

    CPC classification number: G01R1/0735 ,  G01R1/07378 ,  G01R31/2887 ,  H01L21/4853 ,  H01L21/4857 ,  H01L22/30

    Abstract: Flexible film electrical-test substrates with at least one conductive contact post for integrated circuit (IC) bump(s) electrical testing, and related methods and testing apparatuses are disclosed. The backside structure of an electrical-test substrate comprises a flexible dielectric film structure. One or more fine-pitched conductive coupling posts are formed on conductive pads disposed on a front side of the flexible dielectric film structure through a fabrication process. A first pitch of the conductive coupling post(s) in the flexible dielectric film structure is provided to be the same or substantially the same as a second pitch of one or more bumps in an IC, such as die or interposer (e.g., forty (40) micrometers (μm) or less). This allows the conductive coupling post(s) to be placed into mechanical contact with at least one bump of the IC, point-by-point, during an electrical test to electrically testing of the IC.

    Abstract translation: 公开了具有至少一个用于集成电路（IC）凸点电气测试的导电接触柱的柔性膜电测基板及相关方法和测试装置。 电测基板的背面结构包括柔性电介质膜结构。 通过制造工艺，在设置在柔性电介质膜结构的前侧的导电焊盘上形成一个或多个细间距导电耦合柱。 将柔性电介质膜结构中的导电耦合柱的第一间距设置为与IC中的一个或多个凸起的第二间距相同或基本相同，例如模具或插入件（例如，40（ 40微米（μm）以下）。 这允许导电耦合柱在电测试期间被放置成与IC的至少一个凸点相接触，以电IC测试。

    CAPACITOR STRUCTURE WITH ASYMMETRIC TERMINALS
    5.
    发明申请
    CAPACITOR STRUCTURE WITH ASYMMETRIC TERMINALS 审中-公开
    具有不对称端子的电容结构

    公开(公告)号：WO2016200574A1

    公开(公告)日：2016-12-15

    申请号：PCT/US2016/033038

    申请日：2016-05-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： SONG, Young Kyu ,  WE, Hong Bok ,  HWANG, Kyu-Pyung

    IPC: H01G4/30 ,  H01G4/232 ,  H01G2/06

    CPC classification number: H01G4/228 ,  H01G2/065 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30

    Abstract: A passive discrete device (400) includes a first asymmetric terminal (410A) and a second asymmetric terminal (410B). The passive discrete device (400) further includes first internal electrodes (420A) extended to electrically couple to a first side and a second side of the first asymmetric terminal (410A). The passive discrete device (400) also includes second internal electrodes (420B) extended to electrically couple to a first side and a second side of the second asymmetric terminal (420B).

    Abstract translation: 无源分立器件（400）包括第一非对称端子（410A）和第二非对称端子（410B）。 无源分立器件（400）还包括延伸以电耦合到第一非对称端子（410A）的第一侧和第二侧的第一内部电极（420A）。 无源分立器件（400）还包括延伸以电耦合到第二不对称端子（420B）的第一侧和第二侧的第二内部电极（420B）。

    INTEGRATED DEVICE PACKAGE COMPRISING SILICON BRIDGE IN PHOTO IMAGEABLE LAYER
    7.
    发明申请
    INTEGRATED DEVICE PACKAGE COMPRISING SILICON BRIDGE IN PHOTO IMAGEABLE LAYER 审中-公开
    在照相图像层中包含硅桥的集成设备包

    公开(公告)号：WO2016081320A1

    公开(公告)日：2016-05-26

    申请号：PCT/US2015/060700

    申请日：2015-11-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

    IPC: H01L25/065 ,  H01L23/538 ,  H05K3/46

    CPC classification number: H01L23/5385 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H05K3/4694 ,  H05K2203/061 ,  H01L2924/00

    Abstract: An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to the base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge.

    Abstract translation: 集成器件封装包括基部，再分配部分，第一管芯和第二管芯。 基部包括可光成像层，至少部分地嵌入在可照光成像层中的桥，以及可照片成像层中的一组通孔。 桥包括包括第一密度的第一组互连。 该组通孔包括第二密度。 再分配部分耦合到基部。 再分配部分包括耦合到第一组互连的至少一个电介质层，第二组互连以及耦合到该组通孔的第三组互连。 第一管芯耦合到再分配部分。 第二管芯耦合到再分配部分，其中第一管芯和第二管芯通过包括桥的电路相互连接。

    INTEGRATED DEVICE COMPRISING COAXIAL INTERCONNECT
    9.
    发明申请
    INTEGRATED DEVICE COMPRISING COAXIAL INTERCONNECT 审中-公开
    包含同轴互连的集成设备

    公开(公告)号：WO2016007706A1

    公开(公告)日：2016-01-14

    申请号：PCT/US2015/039678

    申请日：2015-07-09

    Applicant: QUALCOMM INCORPORATED

    Inventor： KIM, Dong Wook ,  SONG, Young Kyu ,  HWANG, Kyu-Pyung ,  WE, Hong Bok

    IPC: H01L23/498 ,  H01L21/48

    CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K3/284 ,  H05K3/46 ,  H05K2203/1316

    Abstract: Some novel features pertain to an integrated device that includes a substrate, a first interconnect coupled to the substrate, and a second interconnect surrounding the first interconnect. The second interconnect may be configured to provide an electrical connection to ground. In some implementations, the second interconnect includes a plate. In some implementations, the integrated device also includes a dielectric material between the first interconnect and the second interconnect. In some implementations, the integrated device also includes a mold surrounding the second interconnect. In some implementations, the first interconnect is configured to conduct a power signal in a first direction. In some implementations, the second interconnect is configured to conduct a grounding signal in a second direction. In some implementations, the second direction is different from the first direction. In some implementations, the integrated device may be a package-on-package (PoP) device.

    Abstract translation: 一些新颖的特征涉及包括衬底，耦合到衬底的第一互连和围绕第一互连的第二互连的集成器件。 第二互连可以被配置为提供到地的电连接。 在一些实现中，第二互连包括板。 在一些实施方案中，集成器件还包括在第一互连和第二互连之间的介电材料。 在一些实施方案中，集成装置还包括围绕第二互连的模具。 在一些实现中，第一互连被配置为在第一方向上传导功率信号。 在一些实现中，第二互连被配置为在第二方向上传导接地信号。 在一些实施方式中，第二方向与第一方向不同。 在一些实施方式中，集成器件可以是封装封装（PoP）器件。

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