公开(公告)号：WO2016118292A1

公开(公告)日：2016-07-28

申请号：PCT/US2015/067863

申请日：2015-12-29

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Jae Sik ,  WE, Hong Bok ,  KIM, Dong Wook

IPC: H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2924/0002 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A semiconductor device may include a first semiconductor die. A passivation layer supports the first semiconductor die. The passivation layer may include a first via having a barrier layer and a first redistribution layer (RDL) conductive interconnect coupled to the first via through the barrier layer. The first via may couple the first semiconductor die to the first RDL conductive interconnect.

Abstract translation: 半导体器件可以包括第一半导体管芯。 钝化层支撑第一半导体管芯。 钝化层可以包括具有阻挡层的第一通孔和通过阻挡层耦合到第一通孔的第一再分布层（RDL）导电互连。 第一通孔可以将第一半导体管芯耦合到第一RDL导电互连。

公开(公告)号：WO2015160671A1

公开(公告)日：2015-10-22

申请号：PCT/US2015/025435

申请日：2015-04-10

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  KIM, Chin-Kwan ,  KIM, Dong Wook ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：WO2016179159A1

公开(公告)日：2016-11-10

申请号：PCT/US2016/030543

申请日：2016-05-03

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik

IPC: H01L23/538

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/3157 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/19 ,  H01L24/25 ,  H01L24/27 ,  H01L24/33 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/19 ,  H01L2224/2205 ,  H01L2224/221 ,  H01L2224/24137 ,  H01L2224/24226 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: A semiconductor package according to some examples of the disclosure may include a substrate having a bridge embedded in the substrate, a first and second die coupled to the substrate, and a plurality of electrically conductive bridge interconnects in the substrate coupling the bridge to the first and second die. The plurality of electrically conductive bridge interconnects may have a first bridge contact layer directly coupled to the bridge, a first solder layer on the first bridge contact layer, a second bridge contact layer on the first solder layer, a second solder layer on the second bridge contact layer, and a die contact directly coupled to one of the first and second die where the plurality of electrically conductive bridge interconnects are embedded in the substrate.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括具有嵌入在衬底中的桥的衬底，耦合到衬底的第一和第二裸片以及耦合到第一和第二衬底的衬底中的多个导电桥互连 第二次死亡 多个导电桥互连可以具有直接耦合到桥的第一桥接触层，第一桥接触层上的第一焊料层，第一焊料层上的第二桥接触层，第二桥上的第二焊料层 接触层和直接耦合到所述第一和第二管芯中的一个的管芯接触，其中所述多个导电桥互连件嵌入在所述衬底中。

公开(公告)号：WO2016081320A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/060700

申请日：2015-11-13

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC: H01L25/065 ,  H01L23/538 ,  H05K3/46

CPC classification number: H01L23/5385 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H05K3/4694 ,  H05K2203/061 ,  H01L2924/00

Abstract: An integrated device package includes a base portion, a redistribution portion, a first die and a second die. The base portion includes a photo imageable layer, a bridge that is at least partially embedded in the photo imageable layer, and a set of vias in the photo imageable layer. The bridge includes a first set of interconnects comprising a first density. The set of vias includes a second density. The redistribution portion is coupled to the base portion. The redistribution portion includes at least one dielectric layer, a second set of interconnects coupled to the first set of interconnects, and a third set of interconnects coupled to the set of vias. The first die is coupled to the redistribution portion. The second die is coupled to the redistribution portion, where the first die and the second die are coupled to each other through an electrical path that includes the bridge.

Abstract translation: 集成器件封装包括基部，再分配部分，第一管芯和第二管芯。 基部包括可光成像层，至少部分地嵌入在可照光成像层中的桥，以及可照片成像层中的一组通孔。 桥包括包括第一密度的第一组互连。 该组通孔包括第二密度。 再分配部分耦合到基部。 再分配部分包括耦合到第一组互连的至少一个电介质层，第二组互连以及耦合到该组通孔的第三组互连。 第一管芯耦合到再分配部分。 第二管芯耦合到再分配部分，其中第一管芯和第二管芯通过包括桥的电路相互连接。

公开(公告)号：WO2015171636A1

公开(公告)日：2015-11-12

申请号：PCT/US2015/029280

申请日：2015-05-05

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik ,  GU, Shiqun ,  RADOJCIC, Ratibor

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

Abstract translation: 提供具有增加的宽度的衬底块。 衬底块包括两个衬底条，并且衬底条各自包括衬底和穿过衬底的多个填充的通孔。 衬底块可以用于制造封装衬底，并且这些封装衬底可以并入PoP结构中。 封装衬底包括具有多个垂直互连的载体和耦合到垂直互连的条。

公开(公告)号：WO2015134638A1

公开(公告)日：2015-09-11

申请号：PCT/US2015/018784

申请日：2015-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Dong Wook ,  WE, Hong Bok ,  LEE, Jae Sik ,  GU, Shiqun

IPC: H01L23/538 ,  H01L21/56

CPC classification number: H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/24137 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1815 ,  H01L2924/014

Abstract: An integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (206) coupled to a first surface of the base portion, and an underfill (222) between the first die and the base portion. The base portion includes a dielectric layer (202), and a set of redistribution metal layers (230-260). In some implementations, the integrated device further includes an encapsulation material (220) that encapsulates the first die. In some implementations, the integrated device further includes a second die (208) coupled to the first surface of the base portion. In some implementations, the integrated device further includes a set of interconnects (280) on the base portion, the set of interconnects coupling the first die and the second die. In some implementations, the first die includes a first set of interconnect pillars (216) and the second die includes a second set of interconnect pillars (218).

Abstract translation: 一种集成器件（例如集成封装），其包括用于集成器件的基座部分，耦合到基座部分的第一表面的第一管芯（206）和第一管芯与基部之间的底部填充物（222）。 基部包括电介质层（202）和一组再分布金属层（230-260）。 在一些实施方案中，集成器件还包括封装第一裸片的封装材料（220）。 在一些实施方案中，集成装置还包括耦合到基部的第一表面的第二管芯（208）。 在一些实施方案中，集成器件还包括在基部上的一组互连（280），该组互连件将第一管芯和第二管芯连接。 在一些实施方案中，第一管芯包括第一组互连柱（216），并且第二管芯包括第二组互连柱（218）。

公开(公告)号：WO2015134279A1

公开(公告)日：2015-09-11

申请号：PCT/US2015/017802

申请日：2015-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  LEE, Jae Sik ,  GU, Shiqun

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/426 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L2224/18 ,  H05K1/0306 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0094

Abstract: A substrate includes a plurality of vias (210) that are lined with dielectric polymer (215) having a substantially uniform thickness. This substantial uniform thickness provides a lumen within each dielectric-polymer-layer-lined via that is substantially centered within the via. Subsequent deposition of metal (220) into the lumen for each dielectric-polymer-layer-lined via thus provides conductive vias having substantially centered metal conductors.

Abstract translation: 衬底包括多个具有基本上均匀厚度的介电聚合物（215）的通孔（210）。 这个基本上均匀的厚度提供了在每个介质聚合物层衬里的通孔内的管腔，其基本上位于通孔内。 随后将金属（220）沉积到每个介电聚合物层衬里的通孔的内腔中由此提供具有基本中心的金属导体的导电通孔。

公开(公告)号：WO2017019866A1

公开(公告)日：2017-02-02

申请号：PCT/US2016/044487

申请日：2016-07-28

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  LEE, Jae Sik ,  KIM, Dong Wook ,  GU, Shiqun

IPC: H01L21/60 ,  H01L23/538 ,  H01L23/13 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L21/52 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package-on-package (POP) structure is disclosed. The POP structure includes a first die (116), a second die (156), and a photo-imaged dielectric (PID) layer (124). The PID layer is disposed between the first die and the second die. The POP structure also includes a first conductive path (162,182) from the first die through the PID layer to the second die. The first conductive path extends directly through a first area of the PID layer directly between the first die and the second die. The POP structure further includes a second conductive path (103) from the first die through the PID layer to the second die. A particular portion (113) of the second conductive path is perpendicular to the first conductive path and extends through a second area of the PID layer not directly between the first die and the second die.

Abstract translation: 公开了一种封装封装（POP）结构。 POP结构包括第一管芯（116），第二管芯（156）和光电成像介质（PID）层124。 PID层设置在第一管芯和第二管芯之间。 POP结构还包括从第一管芯通过PID层到第二管芯的第一导电路径（162,182）。 第一导电路径直接在第一管芯和第二管芯之间直接延伸通过PID层的第一区域。 POP结构还包括从第一管芯通过PID层到第二管芯的第二导电路径（103）。 第二导电路径的特定部分（113）垂直于第一导电路径并且不直接在第一管芯和第二管芯之间延伸穿过PID层的第二区域。

公开(公告)号：WO2016049454A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/052217

申请日：2015-09-25

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Dong Wook ,  LEE, Jae Sik ,  WE, Hong Bok ,  SONG, Young Kyu ,  KIM, Chin-Kwan ,  HWANG, Kyu-Pyung ,  GU, Shiqun

IPC: H01L23/538 ,  H01L21/60 ,  H10L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: A semiconductor package according to some examples of the disclosure may include a base (110) with a first redistribution layer (150) on one side, first (120) and second (130) side-by-side die attached to the base on an opposite side from the first redistribution layer, an interposer (140) attached to active sides of the first and second die to provide an interconnection between the first and second die, a plurality of die vias (180,181) extending from the first and second die to a second redistribution layer (170) on a surface of the package opposite the first redistribution layer, and a plurality of package vias (182) extending through the package between the first and second redistribution layers.

Abstract translation: 根据本公开的一些示例的半导体封装可以包括在一侧上具有第一再分布层（150）的基座（110），第一（120）和第二（130）并排模具，其在一个 附接到第一和第二管芯的有源侧的插入件（140），以提供第一和第二管芯之间的互连;从第一和第二管芯延伸到多个管道通孔（180,181） 在与所述第一再分配层相对的所述封装的表面上的第二再分配层（170）以及在所述第一和第二再分布层之间延伸穿过所述封装的多个封装通孔（182）。

公开(公告)号：WO2016048626A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/048539

申请日：2015-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Young Kyu ,  WE, Hong Bok ,  KIM, Dong Wook ,  KIM, Chin-Kwan ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  KANG, Seung, Hyuk

IPC: G01R1/073

CPC classification number: G01R1/0735 ,  G01R1/07378 ,  G01R31/2887 ,  H01L21/4853 ,  H01L21/4857 ,  H01L22/30

Abstract: Flexible film electrical-test substrates with at least one conductive contact post for integrated circuit (IC) bump(s) electrical testing, and related methods and testing apparatuses are disclosed. The backside structure of an electrical-test substrate comprises a flexible dielectric film structure. One or more fine-pitched conductive coupling posts are formed on conductive pads disposed on a front side of the flexible dielectric film structure through a fabrication process. A first pitch of the conductive coupling post(s) in the flexible dielectric film structure is provided to be the same or substantially the same as a second pitch of one or more bumps in an IC, such as die or interposer (e.g., forty (40) micrometers (μm) or less). This allows the conductive coupling post(s) to be placed into mechanical contact with at least one bump of the IC, point-by-point, during an electrical test to electrically testing of the IC.

Abstract translation: 公开了具有至少一个用于集成电路（IC）凸点电气测试的导电接触柱的柔性膜电测基板及相关方法和测试装置。 电测基板的背面结构包括柔性电介质膜结构。 通过制造工艺，在设置在柔性电介质膜结构的前侧的导电焊盘上形成一个或多个细间距导电耦合柱。 将柔性电介质膜结构中的导电耦合柱的第一间距设置为与IC中的一个或多个凸起的第二间距相同或基本相同，例如模具或插入件（例如，40（ 40微米（μm）以下）。 这允许导电耦合柱在电测试期间被放置成与IC的至少一个凸点相接触，以电IC测试。