公开(公告)号：US20170101309A1

公开(公告)日：2017-04-13

申请号：US15386014

申请日：2016-12-21

Applicant: QUALCOMM INCORPORATED

Inventor： Michael A. Stuber

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B7/008 ,  B81B2203/0127 ,  B81C1/00269 ,  B81C2201/0194 ,  B81C2203/037 ,  H01L21/2007 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/7806 ,  H01L21/84 ,  H01L23/481 ,  H01L25/00 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2224/9202 ,  H01L2924/00

Abstract: A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes.

公开(公告)号：US09570558B2

公开(公告)日：2017-02-14

申请号：US14855652

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Christopher N. Brindle ,  Michael A. Stuber ,  Stuart B. Molin

IPC: H01L21/30 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L29/1083 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/30 ,  H01L21/30604 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/528 ,  H01L24/09 ,  H01L24/83 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/08145 ,  H01L2224/27452 ,  H01L2224/27616 ,  H01L2224/80001 ,  H01L2224/838 ,  H01L2225/06548 ,  H01L2924/0002 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/00

Abstract: An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer.

Abstract translation: 集成电路芯片形成有活性层和富集层。 有源层由有源器件层和金属互连层形成。 陷阱富层形成在有源层上方。 在一些实施例中，有源层包括在半导体晶片中，并且阱富层包含在处理晶片中。

公开(公告)号：US09558951B2

公开(公告)日：2017-01-31

申请号：US14043764

申请日：2013-10-01

Applicant: QUALCOMM Incorporated

Inventor： Anton Arriagada ,  Chris Brindle ,  Michael A. Stuber

IPC: H01L21/46 ,  H01L21/302 ,  H01L21/20 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L21/302 ,  H01L21/2007 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/80001 ,  H01L2224/9202

Abstract: An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias.

Abstract translation: 集成电路芯片形成有电路层，阱富层和贯通半导体通孔。 陷阱富层形成在电路层上。 贯通半导体通孔也形成在电路层的上方。 在一些实施例中，电路层被包括在晶片中，并且阱富层和贯穿半导体通孔被包括在另一个晶片中。 在形成富集陷阱层和通过半导体通孔之后，两个晶片结合在一起。 另外，在一些实施例中，另一个晶片也可以结合到晶片上，该晶片包括陷阱富集层和贯穿半导体通路。 此外，在一些实施例中，可以在晶片中形成另外的电路层，其中包括阱富层和贯通半导体通路。

公开(公告)号：US09478507B2

公开(公告)日：2016-10-25

申请号：US14596515

申请日：2015-01-14

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber

IPC: H01L23/52 ,  H01L21/70 ,  H01L23/48 ,  H01L29/40 ,  H01L23/60 ,  H01L21/84 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L23/60 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer. The third electrically conductive interconnect layer forms a second electrically conductive plate below the electrically conductive ring and the region of the semiconductor layer. The plurality of electrically conductive vias electrically couple the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate. The electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device.

Abstract translation: 集成电路组件形成有绝缘层，半导体层，有源器件，第一，第二和第三导电互连层以及多个导电通孔。 绝缘层具有第一表面和第二表面。 第二个表面位于第一个表面之下。 衬底层已经从第二表面去除。 半导体层具有第一表面和第二表面。 半导体层的第一表面接触绝缘层的第一表面。 有源器件形成在半导体层的区域中。 第一导电互连层形成导电环。 第二导电互连层在导电环和半导体层的区域之上形成第一导电板。 第三导电互连层在导电环和半导体层的区域之下形成第二导电板。 多个导电通孔将导电环电耦合到第一导电板和第二导电板。 导电环，第一导电板，第二导电板和多个导电通孔围绕有源器件形成法拉第笼。

公开(公告)号：US10079230B2

公开(公告)日：2018-09-18

申请号：US15240009

申请日：2016-08-18

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber ,  Stuart B. Molin

IPC: H01L29/66 ,  H01L27/082 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L27/088 ,  H01L29/06 ,  H01L21/683 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L23/00

CPC classification number: H01L27/0823 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/481 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/088 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7317 ,  H01L29/732 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/781 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/05638 ,  H01L2224/1148 ,  H01L2224/1302 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/48 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2924/01014 ,  H01L2924/00

Abstract: A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers.

公开(公告)号：US09780117B2

公开(公告)日：2017-10-03

申请号：US14521327

申请日：2014-10-22

Applicant: QUALCOMM Incorporated

Inventor： Paul A. Nygaard ,  Michael A. Stuber

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/265 ,  H01L21/3205 ,  H01L21/84 ,  H01L27/06 ,  H01L29/10 ,  H01L29/32 ,  H01L29/47 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L27/1203 ,  H01L21/265 ,  H01L21/32053 ,  H01L21/84 ,  H01L27/0629 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66477 ,  H01L29/7839 ,  H01L29/78612 ,  H01L29/872

Abstract: A semiconductor structure is formed with an active layer having an active device including a body region. The active device is formed by top side processing in and on a top side of a semiconductor on insulator wafer. A damaged region is formed within a portion of the body region by bottom side processing at a bottom side of the semiconductor on insulator wafer, the damaged region having a structure sufficient to prevent a kink effect and self-latching in operation of the active device.

公开(公告)号：US09754860B2

公开(公告)日：2017-09-05

申请号：US14326304

申请日：2014-07-08

Applicant: QUALCOMM Incorporated

Inventor： Stuart B. Molin ,  Michael A. Stuber ,  Mark Drucker

IPC: H01L23/48 ,  H01L21/20 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L21/322 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L23/481 ,  H01L21/2007 ,  H01L21/3221 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/13

Abstract: A semiconductor structure is formed with first and second semiconductor wafers and a redistribution layer. The first semiconductor wafer is formed with a first active layer and a first interconnect layer. The second semiconductor wafer is formed with a second active layer and a second interconnect layer. The second semiconductor wafer is inverted and bonded to the first semiconductor wafer, and a substrate is removed from the second semiconductor wafer. The redistribution layer redistributes electrical connective pad locations on a side of the second semiconductor wafer. The redistribution layer also electrically contacts the first interconnect layer through a hole in the second active layer and the second interconnect layer.

公开(公告)号：US09673219B2

公开(公告)日：2017-06-06

申请号：US14576122

申请日：2014-12-18

Applicant: QUALCOMM Incorporated

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/8234 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L29/78 ,  H01L21/683 ,  H01L21/84 ,  H01L29/73 ,  H01L23/00 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/823487 ,  H01L21/84 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

公开(公告)号：US09647209B2

公开(公告)日：2017-05-09

申请号：US15164540

申请日：2016-05-25

Applicant: QUALCOMM Incorporated

Inventor： Sinan Goktepeli ,  Michael A. Stuber

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1206 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/1608 ,  H01L45/1675

Abstract: Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.

公开(公告)号：US09576937B2

公开(公告)日：2017-02-21

申请号：US15130721

申请日：2016-04-15

Applicant: QUALCOMM INCORPORATED

Inventor： Michael A. Stuber ,  Stuart B. Molin

IPC: H01L25/065 ,  H01L21/78 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/80006 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80 ,  H01L2224/83

Abstract: An integrated circuit assembly includes a first substrate and a second substrate, with active layers formed on the first surfaces of each substrate, and with the second surfaces of each substrate coupled together. A method of fabricating an integrated circuit assembly includes forming active layers on the first surfaces of each of two substrates, and coupling the second surfaces of the substrates together.

Abstract translation: 集成电路组件包括第一衬底和第二衬底，其中有源层形成在每个衬底的第一表面上，并且每个衬底的第二表面耦合在一起。 制造集成电路组件的方法包括在两个基板中的每一个的第一表面上形成有源层，并将基板的第二表面联接在一起。