公开(公告)号：WO2014120389A1

公开(公告)日：2014-08-07

申请号：PCT/US2014/010231

申请日：2014-01-03

Applicant: QUALCOMM INCORPORATED

Inventor： YU, Yang ,  CHIEN, Wei-Jung ,  WANG, Xianglin ,  KARCZEWICZ, Marta

IPC: H04N19/19 ,  H04N19/176 ,  H04N19/147 ,  H04N19/11

CPC classification number: H04N19/11 ,  H04N19/147 ,  H04N19/176 ,  H04N19/19 ,  H04N19/50

Abstract: In general, techniques are described for reducing the complexity of mode selection when selecting from multiple, different prediction modes. A video coding device comprising a processor may perform the techniques. The processor may compute approximate costs for a pre-defined set of intra-prediction modes identified in a current set. The current set of intra-prediction modes may include fewer modes than a total number of intra-prediction modes. The processor may compare approximate costs computed for one or more most probable intra-prediction modes to a threshold and replace one or more of the intra-prediction modes of the current set with one or more most probable intra-prediction modes. The processor may perform rate distortion analysis with respect to each intra-prediction mode identified in the current set and perform intra-prediction coding with respect to the current block using a mode of the current set.

Abstract translation: 一般来说，描述了当从多种不同的预测模式进行选择时降低模式选择的复杂度的技术。 包括处理器的视频编码装置可以执行这些技术。 处理器可以计算在当前集合中识别的预定义的帧内预测模式集合的近似成本。 当前的帧内预测模式集合可以包括比总内帧数据预测模式少的模式。 处理器可以将针对一个或多个最可能的帧内预测模式计算的近似成本与阈值进行比较，并用一个或多个最可能的帧内预测模式来替换当前集合的一个或多个帧内预测模式。 处理器可以针对当前集合中识别的每个帧内预测模式执行速率失真分析，并使用当前集合的模式对当前块执行帧内预测编码。

公开(公告)号：WO2013154747A1

公开(公告)日：2013-10-17

申请号：PCT/US2013/031596

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： YU, Yang ,  COBAN, Muhammed Zeyd ,  KARCZEWICZ, Marta

IPC: H04N7/26

CPC classification number: H04N19/126 ,  H04N19/147 ,  H04N19/149 ,  H04N19/172 ,  H04N19/18

Abstract: A computing device, such as a video encoder, determines an initial quantized level for a coefficient of a coefficient block and determines whether the coefficient is less than the product of the initial quantized level and a quantization step size value. In response to determining that the coefficient is less than the product of the initial quantized level and the quantization step size value, the computing device determines rate-distortion costs of quantizing the coefficient to be the initial quantized level for the coefficient, the initial quantized level minus one, and in some circumstances, 0. The computing device determines an actual quantized level for the coefficient based at least in part on the calculated rate-distortion costs and includes the actual quantized level in a quantized version of the coefficient block.

Abstract translation: 诸如视频编码器的计算设备确定系数块系数的初始量化电平，并确定该系数是否小于初始量化电平与量化步长值的乘积。 响应于确定系数小于初始量化电平和量化步长值的乘积，计算装置确定将系数量化为系数的初始量化电平的速率失真成本，初始量化电平 在一些情况下，在一些情况下，计算装置至少部分地基于所计算的速率失真成本来确定系数的实际量化级别，并且包括系数块的量化版本中的实际量化级别。

公开(公告)号：EP2839640A1

公开(公告)日：2015-02-25

申请号：EP13713026.6

申请日：2013-03-14

Applicant: Qualcomm Incorporated

Inventor： YU, Yang ,  COBAN, Muhammed Zeyd ,  KARCZEWICZ, Marta

IPC: H04N7/26

CPC classification number: H04N19/126 ,  H04N19/147 ,  H04N19/149 ,  H04N19/172 ,  H04N19/18

Abstract: A computing device, such as a video encoder, determines an initial quantized level for a coefficient of a coefficient block and determines whether the coefficient is less than the product of the initial quantized level and a quantization step size value. In response to determining that the coefficient is less than the product of the initial quantized level and the quantization step size value, the computing device determines rate-distortion costs of quantizing the coefficient to be the initial quantized level for the coefficient, the initial quantized level minus one, and in some circumstances, 0. The computing device determines an actual quantized level for the coefficient based at least in part on the calculated rate-distortion costs and includes the actual quantized level in a quantized version of the coefficient block.

公开(公告)号：EP2837177A1

公开(公告)日：2015-02-18

申请号：EP13716683.1

申请日：2013-04-02

Applicant: Qualcomm Incorporated

Inventor： CHEN, Ying ,  ZHANG, Li ,  YU, Yang ,  VAN DER AUWERA, Geert ,  LI, Xiang ,  KARCZEWICZ, Marta

IPC: H04N7/26 ,  H04N7/32

CPC classification number: H04N13/161 ,  H04N19/109 ,  H04N19/176 ,  H04N19/597 ,  H04N19/70

Abstract: A video encoder signals, in a bitstream, a syntax element that indicates whether a current video unit is predicted from a VSP picture. The current video unit is a macroblock or a macroblock partition. The video encoder determines, based at least in part on whether the current video unit is predicted from the VSP picture, whether to signal, in the bitstream, motion information for the current video unit. A video decoder decodes the syntax element from the bitstream and determines, based at least in part on the syntax element, whether the bitstream includes the motion information.

Abstract translation: 视频编码器在比特流中用信号指示语音元素，其指示是否从VSP图像预测当前视频单元。 当前视频单元是宏块或宏块分区。 视频编码器至少部分地基于从VSP图像预测当前视频单元，确定在比特流中是否发送当前视频单元的运动信息。 视频解码器从比特流解码语法元素，并且至少部分地基于语法元素确定比特流是否包括运动信息。

公开(公告)号：EP4402556A1

公开(公告)日：2024-07-24

申请号：EP22764976.1

申请日：2022-08-10

Applicant: QUALCOMM INCORPORATED

Inventor： YU, Yang ,  BARKER, Scott ,  KIES, Jonathan

IPC: G06F3/01 ,  G06F3/03 ,  G06T19/00 ,  G06T7/70

CPC classification number: G06F3/011 ,  G06F3/012 ,  G06F3/0304 ,  G06T19/006 ,  G06V20/20 ,  G06V10/44 ,  G06T2207/1002120130101 ,  G06T2207/1002420130101 ,  G06T7/246 ,  G06T2207/3024420130101

公开(公告)号：EP4241230A1

公开(公告)日：2023-09-13

申请号：EP20960468.5

申请日：2020-11-09

Applicant: QUALCOMM INCORPORATED

Inventor： ZHANG, Yibin ,  YING, Zilin ,  DU, Yun ,  QI, Heng ,  YU, Jiexia ,  YU, Yang ,  GRUBER, Andrew, Evan ,  LIANG, Jian ,  WANG, Tao ,  BOURD, Alexei Vladimirovich ,  ZHONG, Gang ,  HUANG, Minjie

IPC: G06T1/00

公开(公告)号：EP2837177B1

公开(公告)日：2018-08-08

申请号：EP13716683.1

申请日：2013-04-02

Applicant: Qualcomm Incorporated

Inventor： CHEN, Ying ,  ZHANG, Li ,  YU, Yang ,  VAN DER AUWERA, Geert ,  LI, Xiang ,  KARCZEWICZ, Marta

IPC: H04N19/597 ,  H04N19/176 ,  H04N19/70 ,  H04N19/109

CPC classification number: H04N13/161 ,  H04N19/109 ,  H04N19/176 ,  H04N19/597 ,  H04N19/70

Abstract: A video encoder signals, in a bitstream, a syntax element that indicates whether a current video unit is predicted from a VSP picture. The current video unit is a macroblock or a macroblock partition. The video encoder determines, based at least in part on whether the current video unit is predicted from the VSP picture, whether to signal, in the bitstream, motion information for the current video unit. A video decoder decodes the syntax element from the bitstream and determines, based at least in part on the syntax element, whether the bitstream includes the motion information.

公开(公告)号：EP3120554A2

公开(公告)日：2017-01-25

申请号：EP15763665.5

申请日：2015-03-12

Applicant: Qualcomm Incorporated

Inventor： CHONG, In Suk ,  YU, Yang ,  WANG, Xianglin ,  KARCZEWICZ, Marta

IPC: H04N19/42 ,  H04N19/60

CPC classification number: H04N19/60 ,  H04N19/42

Abstract: Systems and methods for low complexity forward transforms using mesh-based calculations are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store video information. The video encoder further comprises a processor in communication with the memory. The processor is configured to decompose a transform into multiple transform stages. The processor is further configured to transform the video information using the multiple stages to determine a transform stage output at each transform stage. The processor is further configured to constrain the transform stage output at each transform stage to a predetermined bit depth. The processor is further configured to perform operations on the constrained transform output of a last stage of the multiple stages, wherein the operations are only available for use with data having the predetermined bit depth.

Abstract translation: 使用基于网格的计算复杂度低正向变换的系统和方法进行了描述英寸 在公开中描述的主题的一个方面提供了一种视频编码器，包括被配置为存储视频信息的存储器。 视频编码器还包括与所述存储器通信的处理器。 所述处理器被配置，以分解变换成多个变换阶段。 所述处理器进一步经配置以变换使用多个阶段确定性矿在每个阶段可变形级输出变换的视频信息。 该处理器被进一步配置来约束每个阶段的变换级输出变换到预定的位深度。 该处理器被进一步配置为在所述多个级的负载级的约束变换输出执行操作，worin的操作是仅适用于与具有预定比特深度数据的使用。

公开(公告)号：EP3120547A2

公开(公告)日：2017-01-25

申请号：EP15763664.8

申请日：2015-03-12

Applicant: Qualcomm Incorporated

Inventor： CHONG, In Suk ,  YU, Yang ,  WANG, Xianglin ,  KARCZEWICZ, Marta

IPC: H04N19/18 ,  H04N19/61 ,  H04N19/176 ,  H04N19/122 ,  H04N19/132

CPC classification number: H04N19/61 ,  H04N19/122 ,  H04N19/132 ,  H04N19/14 ,  H04N19/176 ,  H04N19/18

Abstract: Systems and methods for low complexity forward transforms using zeroed-out coefficients are described herein. One aspect of the subject matter described in the disclosure provides a video encoder comprising a memory configured to store a video block. The video encoder further comprises a processor in communication with the memory. The processor is configured to determine a full power value of the video block. The processor is further configured to determine a reduced transform coefficient matrix, wherein the reduced transform coefficient matrix comprises an inner region of zero or non-zero values of the same inner region of a full transform coefficient matrix and an outer region of zero values, wherein the reduced transform coefficient matrix and the full transform coefficient matrix have the same size. The processor is further configured to determine a partial power value of the video block using the reduced transform coefficient matrix. The processor is further configured to transform the video block from a pixel domain to a coefficient domain using the reduced transform coefficient matrix based on the full power value and partial power value. The processor is further configured to encode the transformed video block.

Abstract translation: 使用归零出系数低复杂度的正向变换的系统和方法进行了描述英寸 在公开中描述的主题的一个方面提供了一种视频编码器，包括被配置为存储视频块的存储器。 视频编码器还包括与所述存储器通信的处理器。 所述处理器被配置为确定矿所述视频块的全功率值。 该处理器被进一步配置为确定矿减小的变换系数矩阵，worin缩小变换和的完整变换系数矩阵的相同的内部区域的零或非零值内部区域的系数矩阵包含在零个值的外部区域中，worin 减小的变换系数矩阵和全变换系数矩阵具有相同的大小。 该处理器被进一步配置为确定矿使用减小的变换系数矩阵中的视频块的局部功率值。 该处理器进一步被配置为使用基于所述全功率值和局部功率值减小的变换系数矩阵从像素域变换视频块的系数的域。 所述处理器进一步经配置以编码所述视频变换块。

公开(公告)号：EP2951996A1

公开(公告)日：2015-12-09

申请号：EP14702664.5

申请日：2014-01-03

Applicant: Qualcomm Incorporated

Inventor： YU, Yang ,  CHIEN, Wei-Jung ,  WANG, Xianglin ,  KARCZEWICZ, Marta

IPC: H04N19/19 ,  H04N19/176 ,  H04N19/147 ,  H04N19/11

CPC classification number: H04N19/11 ,  H04N19/147 ,  H04N19/176 ,  H04N19/19 ,  H04N19/50

Abstract: In general, techniques are described for reducing the complexity of mode selection when selecting from multiple, different prediction modes. A video coding device comprising a processor may perform the techniques. The processor may compute approximate costs for a pre-defined set of intra-prediction modes identified in a current set. The current set of intra-prediction modes may include fewer modes than a total number of intra-prediction modes. The processor may compare approximate costs computed for one or more most probable intra-prediction modes to a threshold and replace one or more of the intra-prediction modes of the current set with one or more most probable intra-prediction modes. The processor may perform rate distortion analysis with respect to each intra-prediction mode identified in the current set and perform intra-prediction coding with respect to the current block using a mode of the current set.

Abstract translation: 通常，描述了当从多个不同的预测模式进行选择时，降低模式选择的复杂度的技术。 包括处理器的视频编码装置可以执行这些技术。 处理器可以计算在当前集合中识别的预定义的帧内预测模式集合的近似成本。 当前的帧内预测模式集合可以包括比帧内预测模式的总数少的模式。 处理器可以将针对一个或多个最可能的帧内预测模式计算的近似成本与阈值进行比较，并用一个或多个最可能的帧内预测模式来替换当前集合的一个或多个帧内预测模式。 处理器可以针对当前集合中识别的每个帧内预测模式执行速率失真分析，并使用当前集合的模式对当前块执行帧内预测编码。