公开(公告)号：GB2140617B

公开(公告)日：1985-06-19

申请号：GB8402263

申请日：1984-01-27

Applicant: RAYTHEON CO

Inventor： FEIST WOLFGANG M

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H01L21/265 ,  H01L29/76

公开(公告)号：CA1025034A

公开(公告)日：1978-01-24

申请号：CA199013

申请日：1974-05-06

Applicant: RAYTHEON CO

Inventor： STATZ HERMAN ,  FEIST WOLFGANG M

IPC: H01J29/45 ,  H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L31/00 ,  H01L31/0216 ,  H01L31/10 ,  A44B1/28

公开(公告)号：CA971615A

公开(公告)日：1975-07-22

申请号：CA171972

申请日：1973-05-23

Applicant: RAYTHEON CO

Inventor： PICKER AMOS ,  FEIST WOLFGANG M

公开(公告)号：CA2070478A1

公开(公告)日：1992-12-28

申请号：CA2070478

申请日：1992-06-04

Applicant: RAYTHEON CO

Inventor： FEIST WOLFGANG M ,  STACEY WILLIAM F

IPC: H01J3/18 ,  H01J1/304 ,  H01J3/02 ,  H01J9/02 ,  H01J1/02

Abstract: A technique for forming field emitters for displays and vacuum microelectronic devices is described. The field emitters include a tip, a grid to control electron emission from the tip, and an electrode for focusing the electron emission. The method avoids simultaneous evaporation at vastly different angles and replaces simultaneous evaporation with successive evaporations followed by a noncritical lift-off.

公开(公告)号：CA2060809A1

公开(公告)日：1992-09-02

申请号：CA2060809

申请日：1992-02-07

Applicant: RAYTHEON CO

Inventor： FEIST WOLFGANG M

IPC: H01J1/304 ,  H01J3/02 ,  H01J3/18 ,  H01J9/02 ,  H01J29/04 ,  H01J29/62 ,  H01J31/12 ,  H01J1/16

Abstract: A field emitter includes an electron emitting structure spaced from an anode structure, with the intervening gap being substantially evacuated. The electron emitting structure includes a first electrically conductive layer spaced by an insulating layer from a second conductive layer, and a generally circular aperture disposed through the layers. The anode structure includes an electrically conductive layer. Electrostatic forces, provided from a potential applied between the first conductive layer and the anode structure, causes an electron beam to be drawn from a cathode provided by a peripheral edge portion of the first conductive layer within the aperture onto an adjacent surface portion of the anode structure. Such field emission occurs under the control of a potential applied between the first and second conductive layers of the electron emitting structure with the second conductive layer functioning as a control electrode of the emitting structure. The anode structure converts the electrical energy from the electron bombardment into visible light energy. In one embodiment, potential applied to a third conductive layer of the emitting structure serves to focus the electron stream on the anode structure. Methods of manufacturing the disclosed electron emitting structures are also described.

公开(公告)号：GB2140616B

公开(公告)日：1985-06-19

申请号：GB8326563

申请日：1983-10-04

Applicant: RAYTHEON CO

Inventor： FEIST WOLFGANG M

IPC: H01L29/80 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H01L29/08 ,  H01L21/265 ,  H01L29/76

公开(公告)号：GB2140617A

公开(公告)日：1984-11-28

申请号：GB8402263

申请日：1984-01-27

Applicant: RAYTHEON CO

Inventor： FEIST WOLFGANG M

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H01L21/265 ,  H01L29/76

Abstract: A method of forming a FET includes the step of forming an elongate buried region 30 below, and spaced from, the gate electrode 44. The buried region is electrically connected to the gate electrode 44 where it breaks through to the electrode at the edges of a mesa layer. The method includes the step of forming a pair of masking strips 14, 16 of insulating material on the surface of the semiconductor. An ion implantation masking layer is formed between the pair of masking strips to enable the selective implantation of particles in the semiconductor to establish the source and drain regions 22, 24. With such method a single masking step is used to define the source, drain and gate regions of the device, namely the masking to define the strips 14 and 16. The buried layer is formed by deep ion implantation with the source and drain masked or without masking so that there is shallow implantation under the strips 14, 16 and deep implantation elsewhere. Gate oxide may be deposited between the strips before implantation. The device may be formed in a semiconducting mesa on a sapphire or similar substrate.

公开(公告)号：GB2140616A

公开(公告)日：1984-11-28

申请号：GB8326563

申请日：1983-10-04

Applicant: RAYTHEON CO

Inventor： FEIST WOLFGANG M

IPC: H01L29/80 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808 ,  H01L29/812 ,  H01L29/08 ,  H01L21/265 ,  H01L29/76

Abstract: A field effect transistor has an elongate buried region 30 of opposite conductivity to the semiconductor layer 12, formed below the gate electrode 44. The buried region which forms a bottom gate is electrically connected to the top gate electrode, where it breaks through to the electrode at the edges of the mesa layer. With this arrangement the channel of the FET has a shallow depth in the semiconductor between the gate electrode 44 and the buried layer 30. The top gate may be of the insulated, schottky or junction type. The FET is fabricated by forming a pair of masking strips 14, 16 of insulating material on the surface of the semiconductor, forming an ion implantation masking layer between the pair of masking strips and implanting particles to establish the source and drain regions 22, 24. With such method a single masking step is used to define the source, drain and gate regions of the device, namely the masking to define the strips 14 and 16. The buried layer is formed by deep ion implantation with the source and drain masked or without masking so that there is shallow implantation under the strips 14, 16 and deep implantation elsewhere. Gate oxide may be deposited between the strips before implantation. The device may be formed in a semiconducting mesa on a sapphire or similar substrate.

公开(公告)号：GB2115609A

公开(公告)日：1983-09-07

申请号：GB8304462

申请日：1983-02-17

Applicant: RAYTHEON CO

Inventor： FEIST WOLFGANG M

IPC: H01L29/73 ,  H01L21/265 ,  H01L21/308 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/302

Abstract: A mask comprising an upper layer 20 and a lower layer 18 of different materials is provided over the surface of a semiconductor structure. A window 21 is formed in the upper layer 20 over the portions of the structure wherein isolation regions are to be provided. Using the window 21 in the upper layer 20 as a mask, a larger window 23 is formed in the lower layer 18 by bringing a chemical etchant which etches only the lower layer into contact with the portions of the lower layer 18 exposed by the window 21 in the upper layer 20. The larger window 23 is used as an etching mask to form an isolation groove 28 in the underlying semiconductor structure. The upper layer 20 is used as an ion implantation mask for implanting particles into the bottom portion of the groove 28 while masking the side portions of the groove 28 from the ions. The grooves 28 are then filled with insulation.

公开(公告)号：CA1144659A

公开(公告)日：1983-04-12

申请号：CA349821

申请日：1980-04-14

Applicant: RAYTHEON CO

Inventor： FEIST WOLFGANG M

IPC: H01L21/8222 ,  H01L21/306 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L27/06 ,  H01L29/10 ,  H01L29/73 ,  H01L29/737 ,  H01L21/461 ,  H01L29/02

Abstract: SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer. A doped polycrystalline silicon layer is formed over the bottom portion of the depression in contact with the active base region to provide an emitter contact for the transistor.