12.
    发明专利
    未知

    公开(公告)号:FR2497037B1

    公开(公告)日:1985-12-27

    申请号:FR8123600

    申请日:1981-12-17

    Applicant: RCA CORP

    Abstract: In a transmission channel, such as a tape recorder, errors in code words usually occur in bursts. Further, it is usually possible to detect only some of the erroneous code words. To conceal undetected erroneous code words, concealment starts before, and continues after, a detected erroneous code word. Thus the undetected erroneous code words in an error burst have a high probability of being concealed.

    13.
    发明专利
    未知

    公开(公告)号:DE3150365A1

    公开(公告)日:1982-09-16

    申请号:DE3150365

    申请日:1981-12-18

    Applicant: RCA CORP

    Abstract: In a transmission channel, such as a tape recorder, errors in code words usually occur in bursts. Further, it is usually possible to detect only some of the erroneous code words. To conceal undetected erroneous code words, concealment starts before, and continues after, a detected erroneous code word. Thus the undetected erroneous code words in an error burst have a high probability of being concealed.

    LINE SCAN CONVERTER FOR AN IMAGE DISPLAY DEVICE

    公开(公告)号:AU3028677A

    公开(公告)日:1979-05-10

    申请号:AU3028677

    申请日:1977-11-03

    Applicant: RCA CORP

    Abstract: The brightness signal for an image display device is digitally processed using an analog to digital converter to translate the signal into digital words. A primary shift register is connected to the output of the analog to digital converter. The primary shift register has a stage capable of containing a digital brightness word for each element in the display line of the device. The primary shift register has a plurality of parallel outputs being spaced X number of stages from each other. Each output is connected to a separate secondary shift register which has X stages.

    DIGITAL MEMORY ADDRESSING SYSTEM
    15.
    发明专利

    公开(公告)号:AU4147878A

    公开(公告)日:1979-05-24

    申请号:AU4147878

    申请日:1978-11-10

    Applicant: RCA CORP

    Abstract: DIGITAL MEMORY ADDRESSING SYSTEM A digital memory may be addressed with an analog signal utilizing a circuit comprising a digital to analog converter. A comparator compares the output of the digital to analog converter to the analog address signal. The output of the comparator is coupled to means for incrementing and decrementing a digital number in response to that output. The digital number incrementing and decrementing means has an output which is coupled to the addressing input of the digital memory. Switch means alternately connects the input of the digital to analog converter to either the output of the random access memory or the output of the means for changing the digital number.

    16.
    发明专利
    未知

    公开(公告)号:DE2849795A1

    公开(公告)日:1979-05-17

    申请号:DE2849795

    申请日:1978-11-16

    Applicant: RCA CORP

    Abstract: DIGITAL MEMORY ADDRESSING SYSTEM A digital memory may be addressed with an analog signal utilizing a circuit comprising a digital to analog converter. A comparator compares the output of the digital to analog converter to the analog address signal. The output of the comparator is coupled to means for incrementing and decrementing a digital number in response to that output. The digital number incrementing and decrementing means has an output which is coupled to the addressing input of the digital memory. Switch means alternately connects the input of the digital to analog converter to either the output of the random access memory or the output of the means for changing the digital number.

    19.
    发明专利
    未知

    公开(公告)号:DE2750343A1

    公开(公告)日:1978-05-11

    申请号:DE2750343

    申请日:1977-11-10

    Applicant: RCA CORP

    Abstract: The brightness signal for an image display device is digitally processed using an analog to digital converter to translate the signal into digital words. A primary shift register is connected to the output of the analog to digital converter. The primary shift register has a stage capable of containing a digital brightness word for each element in the display line of the device. The primary shift register has a plurality of parallel outputs being spaced X number of stages from each other. Each output is connected to a separate secondary shift register which has X stages.

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