公开(公告)号：WO1982003725A1

公开(公告)日：1982-10-28

申请号：PCT/US1982000476

申请日：1982-04-16

Applicant: RCA CORP

Inventor： RCA CORP ,  WILLIS DONALD HENRY

IPC: H01J29/70

CPC classification number: H04N3/185

Abstract: L'enroulement principal (22a, 22b) d'un transformateur d'inductance (22) a perte elevee est couple a une source (19) de tension d'entree (Vp) de courant alternatif pour developper des tensions de sortie de polarite alternee dans des enroulements secondaires couples etroitement les uns aux autres, comprenant un enroulement de haute tension (22c) du transformateur. Plusieurs tensions d'alimentation en courant continu, comprenant la tension d'anode acceleratrice (30KV), sont derivees a partir des tensions de sortie de l'enroulement secondaire. Afin de reguler les tensions de sortie de l'enroulement secondaire, un circuit comprenant un condensateur (23) et une reactance saturable (21) est couple en tant que circuit de charge (20) a un (22F) des enroulements secondaires du transformateur. Lorsque la reactance saturable (21) est magnetiquement saturee pendant chaque demi-cycle de la tension de sortie a polarite alternee, un courant circulant (ic) est produit et s'ecoule entre la reactance saturable (21) et le condensateur (23). Afin d'ameliorer le rendement de l'alimentation de courant et de reduire l'augmentation de temperature a l'interieur du noyau magnetisable (121) de la reactance saturable (21), les parametres du transformateur (22) et du circuit de charge (20) sont selectionnes de maniere a produire un courant circulant possedant une amplitude relativement faible. Afin d'ameliorer la regulation de la tension de sortie lors de la production d'un courant circulant possedant une faible amplitude, on prevoit un enroulement d'attaque de compensation (22g) couple magnetiquement et etroitement au premier enroulement (22a, 22b) du transformateur a fuite elevee (22). L'enroulement d'attaque de compensation (22g) est couple en serie a l'enroulement (21a) de la reactance saturable au travers du condensateur (23) et est polarise par rapport a l'enroulement secondaire (22f) du transformateur couple par condensateur de maniere a s'opposer a la tendance de l'amplitude de la tension de sortie ou de la region volt-seconde de

公开(公告)号：WO1982003518A1

公开(公告)日：1982-10-14

申请号：PCT/US1982000420

申请日：1982-04-05

Applicant: RCA CORP

Inventor： RCA CORP ,  ROBERT ANDREW WARGO

IPC: H04N05/14

CPC classification number: H04N5/21

Abstract: Apparatus which is responsive to a video signal for producing a position-modulated pulse train which is representative of the occurrence of transitions of the video signal. A transversal filter (60) is responsive to the video signal and produces a differentiated replica of the video signal over a given band of frequencies. The output of the transversal filter contains transitional information of the video signal occupying a range of frequencies which is to be analyzed. Information representing transitions of positive, negative, or both polarities is then compared to a given threshold value, generated in threshold generator (82). Signal transitions exceeding the threshold are converted to pulses, thereby producing a train of pulses representing significant transitions of a desired polarity or polarities. The times of occurrence of the pulses are then analyzed to generate a control signal for controlling a given characteristic of the video signal during processing.

Abstract translation: 响应于视频信号以产生位置调制脉冲串的装置，其表示视频信号的转变的发生。 横向滤波器（60）响应于视频信号并且在给定的频带上产生视频信号的差分副本。 横向滤波器的输出包含占据要分析的频率范围的视频信号的过渡信息。 然后，将表示正极性，负极性或两极性的转换的信息与在阈值发生器（82）中生成的给定阈值进行比较。 超过阈值的信号转换被转换为脉冲，从而产生一系列脉冲，表示所需极性或极性的显着转变。 然后分析脉冲的发生次数以产生用于在处理期间控制视频信号的给定特性的控制信号。

公开(公告)号：WO1982003146A1

公开(公告)日：1982-09-16

申请号：PCT/US1982000282

申请日：1982-03-08

Applicant: RCA CORP

Inventor： RCA CORP ,  MEISE WILLIAM HARRY ,  DISCHERT ROBERT ADAMS

IPC: H04N05/14

CPC classification number: H04N5/2176

Abstract: Two or more CCD imagers (12, 14), which have random defects are optically coupled to form a single image. The CCD's are in registry. Because of the random nature of the location of the defects, the defective photosensors of one imager (12) are aligned with good photosensors of another (14). Memories (34, 36) keep track of which locations of which CCD are defective. The imagers (12, 14) are operated synchronously and the signals from good photosensor locations are summed for improved signal-to-noise ratio. When a location is addressed at which one imager (12) has a defective photosensor, the respective memory (34) decouples it from the good photosensor of the other imager (14). The signal level is restored for that location by increasing the gain of a preamp (46) by the correct amount. If the imagers (12, 14) are made from the same mask, they may have almost identically corresponding defective photosensors. Then one imager (12) is mounted upside-down relative to the other (14) and scanned backwards so the defects do not coincide.

Abstract translation: 具有随机缺陷的两个或更多CCD成像器（12,14）被光学耦合以形成单个图像。 CCD的注册表。 由于缺陷的位置的随机性质，一个成像器（12）的有缺陷的光电传感器与另一个成像器的良好光电传感器对准（14）。 记忆（34,36）跟踪CCD哪些位置有缺陷。 成像器（12,14）同步操作，来自良好光电传感器位置的信号相加以提高信噪比。 当位置被寻址到哪个成像器（12）具有有缺陷的光电传感器时，相应的存储器（34）将其与另一个成像器（14）的良好的光电传感器分离。 通过将前置放大器（46）的增益增加正确的量来恢复该位置的信号电平。 如果成像器（12,14）由相同的掩模制成，它们可以具有几乎相同的相应的有缺陷的光电传感器。 然后，一个成像器（12）相对于另一个（14）倒置安装并向后扫描，使得缺陷不一致。

公开(公告)号：WO1979000745A1

公开(公告)日：1979-10-04

申请号：PCT/US1979000130

申请日：1979-03-06

Applicant: RCA CORP ,  BART T ,  MILLS R

Inventor： RCA CORP

IPC: H04N09/02

CPC classification number: H04N9/641 ,  H04N5/45

Abstract: A system employed in a television receiver for decoding and displaying graphics information such as may be encoded on a broadcast video signal. The system includes a graphics decoder (27) supplied with the encoded video signal, and a plurality of transmission ga (31-36) responsive to logic control signals derived from the outputs of the decoder (27). The gates (31-36) are coupled to inputs of video output stages (16) in the receiver, and operate in response to the control signals for interrupting normal video signals to the video output stages (16) and for enabling a voltage representative of a graphics display intensity level to be coupled to the video output stages (16) when graphics information is to be displayed. The system also includes a graphics level control network (25). The level control network (25) limits excessive graphics representative beam current levels to prevent image defocusing and kinescope screen burn. The level control network (25) also adjusts the graphics display intensity level in accordance with the level of image representative video signals in a mixed video plus graphics display mode, to preserve a desired contrast relationship between the displayed video and graphics information.

Abstract translation: 一种用于电视接收机中用于解码和显示诸如可以在广播视频信号上编码的图形信息的系统。 该系统包括提供有编码视频信号的图形解码器（27）和响应于从解码器（27）的输出导出的逻辑控制信号的多个传输ga（31-36）。 栅极（31-36）耦合到接收器中的视频输出级（16）的输入端，并且响应用于中断视频输出级（16）的正常视频信号的控制信号而工作， 当要显示图形信息时，要耦合到视频输出级（16）的图形显示强度级别。 该系统还包括图形级控制网络（25）。 电平控制网络（25）限制了过多的图形代表性的电流电平，以防止图像散焦和显像管屏幕烧伤。 电平控制网络（25）还根据混合视频加图形显示模式中的图像代表性视频信号的电平来调整图形显示强度水平，以保持所显示的视频和图形信息之间的期望的对比度关系。

公开(公告)号：WO1979000169A1

公开(公告)日：1979-04-05

申请号：PCT/US1978000094

申请日：1978-10-02

Applicant: RCA CORP

Inventor： RCA CORP ,  BEYERS B ,  SUCHKO A

IPC: H04N05/44

CPC classification number: H03J5/0263 ,  G04G15/006

Abstract: A television receiver includes a chassis (12) having a digital tuner (14) for generating local oscillator signals for tuning the receiver to respective channels in response to binary signals representing corresponding channel numbers and a signal processing unit (18) for controlling at least one characteristic of the receiver, such as the sound level, in response to binary signals representing the controllable characteristic. The receiver also includes a microcomputer (34) including a RAM (130) (Random Access Memory) with at least one memory location for storing binary signals representing the present time and a plurality of memory locations for storing binary signals representing future times and channel numbers of channels to be tuned at those times. A control portion (100) of the microcomputer causes binary signals representing the channel number associated with a future time to be coupled to the digital tuner when the present time matches the future time. A keyboard (32) having ten digit keys for generating binary signals representing the decimal digits between 0 and 9 and two characteristic keys to generate binary signals representing an increase and a decrease in the controllable characteristic is provided to enable user control of various operating modes of the receiver. When a user operates digit keys to form a number within a predetermined range of channel numbers e.g. 2-83, the control portion of the microcomputer causes the channel to be tuned. Subsequently operation of digit keys within the predetermined range of channel numbers causes the channel to be changed and operation of the characteristic keys causes the controllable characteristic to change. When a user operates digit keys to form a number not within the predetermined range of channel numbers, the control portion of the microcomputer causes power to be decoupled from the chassis. Subsequently, in response to the operation of a predetermined one of the characteristic keys, the control portion causes binary signals generated in response to the operation of the digit keys to be selectively coupled to either the RAM location associated with the present time or to the RAM location for future selections.

公开(公告)号：WO1982002637A1

公开(公告)日：1982-08-05

申请号：PCT/US1982000086

申请日：1982-01-25

Applicant: RCA CORP

Inventor： RCA CORP ,  STROLLE CHRISTOPHER HUGH ,  SMITH TERRANCE RAYMOND ,  LEWIS HENRY GARTON JR ,  ACAMPORA ALFONSE ,  REITMEIER GLENN ARTHUR

IPC: H04N05/02

CPC classification number: H04N9/78 ,  G06F1/0307 ,  G06F1/0353 ,  G06F1/0356 ,  G06F2101/04 ,  G06F2101/08 ,  G06F2101/10 ,  G06T3/00 ,  G09G5/395 ,  G11C7/00 ,  G11C8/04 ,  G11C8/16 ,  H04N9/646

Abstract: A digital memory (10) which contains digital data words representative of a desired symmetrical transfer characteristic of a digital signal processor. Digital signals which are to be processed are applied to the address inputs of the memory (10), producing output signals in conformance with the desired transfer characteristic. Advantage is taken of the symmetrical nature of the response characteristic to minimize the size of the memory. Data words corresponding to only a portion of the full dynamic range of the digital signal processor are stored in the memory (10), and memory locations are addressed and read out in accordance with the value of a polarity-determining bit of the input digital signal, with the output signals being translated over the required full dynamic range in accordance with the value of the polarity-determining bit. In a preferred embodiment of the invention, the memory (10) is a random access memory, with stored data values being altered in response to a user control to change the transfer characteristic of the processor.

Abstract translation: 数字存储器（10），其包含表示数字信号处理器的期望对称传送特性的数字数据字。 要处理的数字信号被施加到存储器（10）的地址输入端，产生符合期望传输特性的输出信号。 利用响应特性的对称性优点来最小化存储器的大小。 仅对应于数字信号处理器的全部动态范围的一部分的数据字被存储在存储器（10）中，并且根据输入数字信号的极性确定位的值来寻址和读出存储单元 ，其中输出信号根据极性确定位的值在所需的全动态范围内转换。 在本发明的优选实施例中，存储器（10）是随机存取存储器，响应于用户控制改变存储的数据值，改变处理器的传送特性。

公开(公告)号：WO1982000394A1

公开(公告)日：1982-02-04

申请号：PCT/US1981000958

申请日：1981-07-15

Applicant: RCA CORP

Inventor： RCA CORP ,  SMITH T ,  MARLOWE F

IPC: H04N05/06

CPC classification number: H04N5/067

Abstract: A television sync signal generator adapted for ready conversion among various television standards includes a memory (216) in which information related to the magnitude of at least one component of a composite sync signal is stored at address locations each corresponding to at least one particular time in each recurrent television frame. A clock signal generator (212) addresses the memory (216) to sequentially read out the information so the sync signal can be reconstructed. By dividing the sync signal into four intervals which are selected by paging signals from one counter, a reduction in required memory capacity is achieved. For further reducing the number of memory addresses required, each memory address contains information relating to the instantaneous resolution or clock rate. A sample rate controller (820) is coupled to the memory for having the instantaneous clock address rate controlled in response to the contents of the memory.

Abstract translation: 适于在各种电视标准之间进行即时转换的电视同步信号发生器包括存储器（216），其中与复合同步信号的至少一个分量的大小相关的信息被存储在地址位置，每个地址位置对应于至少一个特定时间 每个经常性的电视架构。 时钟信号发生器（212）寻址存储器（216）以顺序读出信息，从而可以重构同步信号。 通过将同步信号划分成由来自一个计数器的寻呼信号选择的四个间隔，实现了所需存储器容量的减少。 为了进一步减少所需的存储器地址数量，每个存储器地址包含与瞬时分辨率或时钟速率有关的信息。 采样率控制器（820）耦合到存储器，用于响应于存储器的内容来控制瞬时时钟地址速率。

公开(公告)号：WO1979000905A1

公开(公告)日：1979-11-15

申请号：PCT/US1978000102

申请日：1978-10-06

Applicant: RCA CORP ,  BREITHAUPT D

Inventor： RCA CORP

IPC: H04N05/04

CPC classification number: H04N5/0733

Abstract: In a television camera system, a horizontal synchronizing signal from a reference source (100) is sampled at the vertical rate by a first sampling gate (104) controlled by a vertical rate signal from a reference source (102). A signal related to the output of a horizontal frequency synchronizing pulse generator (E) is sampled at the vertical rate by a second sampling gate (106) controlled by the vertical rate signal. The output of each sampling gate is fed to an input of a phase detector (114) which develops an error signal indicative of the phase relationship between the two sampled signals. The error signal is utilized to control the phase of the generated horizontal synchronizing pulse to synchronize a remote television camera head even though connected by a cable of unknown length.

Abstract translation: 在电视摄像机系统中，来自参考源（100）的水平同步信号通过由来自参考源（102）的垂直速率信号控制的第一采样门（104）以垂直速率进行采样。 与水平频率同步脉冲发生器（E）的输出相关的信号以垂直速率由垂直速率信号控制的第二采样门（106）进行采样。 每个采样门的输出被馈送到相位检测器（114）的输入端，该相位检测器产生指示两个采样信号之间的相位关系的误差信号。 误差信号用于控制所产生的水平同步脉冲的相位，以便即使通过未知长度的电缆连接，也能使远程电视摄像机头同步。

公开(公告)号：WO1979000717A1

公开(公告)日：1979-10-04

申请号：PCT/US1979000099

申请日：1979-02-22

Applicant: RCA CORP ,  ASTLE B ,  DISCHERT R

Inventor： RCA CORP

IPC: H04N09/62

CPC classification number: H04N5/262 ,  H04N9/04 ,  H04N9/093 ,  H04N17/002

Abstract: A system is described for automatic adjustment of a color television camera (14) for correcting for geometrical errors in the raster and amplitude errors in the video. The system includes means (13, 27) for measuring the errors, positions, or amplitudes of the camera output signals at different locations of the red, green, and blue rasters for simultaneously providing detected signals representing the detected error positions or amplitudes of these locations to a signal processing means (24). The processing means (24) selectively and separately processes said detected signals according to a plurality of algorithms for producing a plurality of correction signals. The correction signals are applied (28) to the camera (14) for adjusting the camera according to all of the correction signals before remeasuring the rasters.

公开(公告)号：WO1979000372A1

公开(公告)日：1979-06-28

申请号：PCT/US1978000185

申请日：1978-12-05

Applicant: RCA CORP

Inventor： RCA CORP ,  VILKOMERSON D ,  MEZRICH R

IPC: G01N29/00

CPC classification number: G10K11/345 ,  B06B1/0622 ,  G01N29/06 ,  G01S7/5206 ,  G10K11/004

Abstract: A transducer (102) comprising a longitudinal bar of piezoelectric material (200) having one longitudinal face substantially covered with a first electrode (202) and the opposite longitudinal face in contact with a predetermined plural number of separate electrodes (204-1, 204-2, ... 204-n) spaced along the length thereof, permits all detected echoes to be processed by a single low input impedance amplifier (206) permanently coupled to the first electrode.