公开(公告)号：US20230232612A1

公开(公告)日：2023-07-20

申请号：US18050179

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanwoo Shin ,  Hyuckjin KANG ,  Donghwan LEE ,  Jeonil LEE ,  Minwu KIM ,  Jungwoo SONG

IPC: H01L29/94

CPC classification number: H01L27/10814 ,  H01L27/10885 ,  H01L27/10855

Abstract: A semiconductor device includes a bit line structure on a substrate, a lower contact plug on a portion of the substrate adjacent to the bit line structure, an upper contact plug including a first metal pattern on the lower contact plug and a second metal pattern contacting an upper surface and an upper sidewall of the first metal pattern, and a capacitor on the upper contact plug. The upper surface of the first metal pattern is above an upper surface of the bit line structure with respect to an upper surface of the substrate.

公开(公告)号：US20250125225A1

公开(公告)日：2025-04-17

申请号：US18989035

申请日：2024-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin LEE ,  Jongmin LEE ,  Jeonil LEE

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H10B99/00

Abstract: A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.

公开(公告)号：US20250062193A1

公开(公告)日：2025-02-20

申请号：US18934456

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20240099015A1

公开(公告)日：2024-03-21

申请号：US18368067

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Kyunghwan Lee

IPC: H10B51/20

CPC classification number: H10B51/20 ,  H10B80/00

Abstract: A semiconductor device includes a substrate. A plurality of horizontal structures is stacked on the substrate and spaced apart from each other. A plurality of vertical structures penetrates through the plurality of horizontal structures. Each of the plurality of vertical structures includes a vertical source line, a vertical bit line, a channel layer, and a dielectric layer. The channel layer is in direct contact with the vertical source line and the vertical bit line. The dielectric layer is disposed between the plurality of horizontal structures and the channel layer. Each of the plurality of horizontal structures includes a first conductive layer, a ferroelectric layer surrounding at least a portion of the first conductive layer, and a second conductive layer disposed between the ferroelectric layer and the dielectric layer.

公开(公告)号：US20240098974A1

公开(公告)日：2024-03-21

申请号：US18501576

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil LEE ,  Youngjun KIM ,  Jinbum KIM

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/37 ,  H10B12/482

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

公开(公告)号：US20230116911A1

公开(公告)日：2023-04-13

申请号：US17736212

申请日：2022-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil LEE ,  Jongmin LEE ,  Jimin CHOI ,  Yeonjin LEE

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/535 ,  H01L21/768

Abstract: A semiconductor device includes a substrate including a first surface, and a second surface opposing the first surface. A via insulating layer extending through the substrate is disposed. A through-silicon via extending through the via insulating layer is disposed. The center of the through-silicon via is misaligned from the center of the via insulating layer. A blocking layer is disposed on the first surface. A first insulating layer is disposed on the blocking layer. A contact plug contacting the through-silicon via and extending through the first insulating layer and the blocking layer is disposed.

公开(公告)号：US20230077803A1

公开(公告)日：2023-03-16

申请号：US17751740

申请日：2022-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jimin CHOI ,  Jongmin LEE ,  Yeonjin LEE ,  Jeonil LEE ,  Juik LEE ,  Minjung CHOI

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, an etch stop layer on the substrate, a through-hole electrode extending through the substrate and the etch stop layer in a vertical direction substantially perpendicular to an upper surface of the substrate, and a conductive pad. The etch stop layer includes a first surface adjacent to the substrate and a second surface opposite the first surface. The through-hole electrode includes a protrusion portion that protrudes from the second surface of the etch stop layer. The conductive pad covers the protrusion portion of the through-hole electrode. The protrusion portion of the through-hole electrode is not flat.

公开(公告)号：US20230005818A1

公开(公告)日：2023-01-05

申请号：US17574902

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeonjin LEE ,  Jongmin LEE ,  Jeonil LEE

IPC: H01L23/48 ,  H01L27/105 ,  H01L21/768 ,  H01L25/065

Abstract: A semiconductor device according to some example embodiments includes a substrate, an insulating structure covering the substrate, a transistor between the substrate and the insulating structure, a via insulating layer extending through the insulating structure and the substrate, a plurality of via structures extending through the via insulating layer, a plurality of conductive structures respectively connected to the plurality of via structures, and a plurality of bumps respectively connected to the conductive structures.